Datasheet

ADS8320
10
SBAS108D
www.ti.com
SYMBOL DESCRIPTION MIN TYP MAX UNITS
t
SMPL
Analog Input Sample Time 4.5 5.0 Clk Cycles
t
CONV
Conversion Time 16 Clk Cycles
t
CYC
Throughput Rate 100 kHz
t
CSD
CS Falling to 0 ns
DCLOCK LOW
t
SUCS
CS Falling to 20 ns
DCLOCK Rising
t
hDO
DCLOCK Falling to 5 15 ns
Current D
OUT
Not Valid
t
dDO
DCLOCK Falling to Next 30 50 ns
D
OUT
Valid
t
dis
CS Rising to D
OUT
Tri-State 70 100 ns
t
en
DCLOCK Falling to D
OUT
20 50 ns
Enabled
t
f
D
OUT
Fall Time 5 25 ns
t
r
D
OUT
Rise Time 7 25 ns
FIGURE 3. ADS8320 Basic Timing Diagrams.
TABLE I. Timing Specifications (V
CC
= 2.7V and above,
–40°C to +85°C.
DESCRIPTION ANALOG VALUE
Full-Scale Range V
REF
Least Significant V
REF
/65,536
Bit (LSB) BINARY CODE HEX CODE
Full-Scale V
REF
– 1 LSB 1111 1111 1111 1111 FFFF
Midscale V
REF
/2 1000 0000 0000 0000 8000
Midscale – 1LSB V
REF
/2 – 1 LSB 0111 1111 1111 1111 7FFF
Zero 0V 0000 0000 0000 0000 0000
DIGITAL OUTPUT
STRAIGHT BINARY
TABLE II. Ideal Input Voltages and Output Codes.
SERIAL INTERFACE
The ADS8320 communicates with microprocessors and other
digital systems via a synchronous 3-wire serial interface, as
shown in Figure 3 and Table I. The DCLOCK signal syn-
chronizes the data transfer with each bit being transmitted on
the falling edge of DCLOCK. Most receiving systems will
capture the bitstream on the rising edge of DCLOCK. How-
ever, if the minimum hold time for D
OUT
is acceptable, the
system can use the falling edge of DCLOCK to capture each
bit.
A falling CS signal initiates the conversion and data transfer.
The first 4.5 to 5.0 clock periods of the conversion cycle are
used to sample the input signal. After the fifth falling
DCLOCK edge, D
OUT
is enabled and outputs a LOW value
for one clock period. For the next 16 DCLOCK periods,
D
OUT
outputs the conversion result, most significant bit first.
After the least significant bit (B0) has been output, subse-
quent clocks repeat the output data but in a least significant
bit first format.
After the most significant bit (B15) has been repeated, D
OUT
will tri-state. Subsequent clocks will have no effect on the
converter. A new conversion is initiated only when CS has
been taken HIGH and returned LOW.
DATA FORMAT
The output data from the ADS8320 is in Straight Binary
format, as shown in Table II. This table represents the ideal
output code for the given input voltage and does not include
the effects of offset, gain error, or noise.
POWER DISSIPATION
The architecture of the converter, the semiconductor fabrica-
tion process, and a careful design allow the ADS8320 to
convert at up to a 100kHz rate while requiring very little
power. Still, for the absolute lowest power dissipation, there
are several things to keep in mind.
The power dissipation of the ADS8320 scales directly with
conversion rate. Therefore, the first step to achieving the
lowest power dissipation is to find the lowest conversion
rate that satisfies the requirements of the system.
In addition, the ADS8320 is in power-down mode under two
conditions: when the conversion is complete and whenever
CS is HIGH (as shown in Figure 3). Ideally, each conversion
should occur as quickly as possible, preferably at a 2.4MHz
clock rate. This way, the converter spends the longest
possible time in the power-down mode. This is very impor-
tant as the converter not only uses power on each DCLOCK
transition (as is typical for digital CMOS components), but
also uses some current for the analog circuitry, such as the
comparator. The analog section dissipates power continu-
ously, until the power-down mode is entered.
CS/SHDN
D
OUT
DCLOCK
Complete Cycle
Power Down
ConversionSample
Use positive clock edge for data transfer
t
SUCS
t
CONV
t
SMPL
NOTE: Minimum 22 clock cycles required for 16-bit conversion. Shown are 24 clock cycles.
If CS remains LOW at the end of conversion, a new datastream with LSB-first is shifted out again.
B15
(MSB)
B14 B13 B12 B11 B10 B9 B8 B0
(LSB)
B7 B1B6 B2B5 B3B4
Hi-Z
0
Hi-Z
t
CSD