Datasheet
ADS8319
www.ti.com
SLAS600A –MAY 2008–REVISED SEPTEMBER 2013
TIMING REQUIREMENTS
All specifications typical at –40°C to 85°C, +VA = 5 V, +VBD ≥ 4.5 V
PARAMETER REF FIGURE MIN TYP MAX UNIT
SAMPLING AND CONVERSION RELATED
t
acq
Acquisition time 600 ns
Figure 46, Figure 48, Figure 50,
t
cnv
Conversion time 1400 ns
Figure 52
t
cyc
Time between conversions 2000 ns
t
1
Pulse duration, CONVST high Figure 46, Figure 48 10 ns
t
6
Pulse duration, CONVST low Figure 50, Figure 52, Figure 54 20 ns
I/O RELATED
t
clk
SCLK Period 20 ns
t
clkl
SCLK Low time 9 ns
Figure 46, Figure 48, Figure 50,
t
clkh
SCLK High time 9 ns
Figure 52, Figure 54, Figure 56
t
2
SCLK Falling edge to data remains valid 5 ns
t
3
SCLK Falling edge to next data valid delay 16 ns
t
en
Enable time, CONVST or SDI Low to MSB valid Figure 46, Figure 50 15 ns
Disable time, CONVST or SDI high or last SCLK falling edge Figure 46, Figure 48, Figure 50,
t
dis
12 ns
to SDO 3-state (CS mode) Figure 52
t
4
Setup time, SDI valid to CONVST rising edge 5 ns
Figure 50, Figure 52
t
5
Hold time, SDI valid from CONVST rising edge 5 ns
t
7
Setup time, SCLK valid to CONVST rising edge 5 ns
Figure 54
t
8
Hold time, SCLK valid from CONVST rising edge 5 ns
Copyright © 2008–2013, Texas Instruments Incorporated Submit Documentation Feedback 5
Product Folder Links: ADS8319