Datasheet

2 3
16
17
CONVST
ACQUISITION
CONVERSION
ACQUISITION
SCLK
SDO #2
t
7
t
2
t
3
t
clkh
t
clkl
t
clk
18
19
32
33
#1-D15 #1-D14 #1-D1
#1-D0
#2-D15
#2-D14
#2-D1
#2-D0
SDO #1, SDI #2
#1-D15 #1-D14
#1-D1
#1-D0
1
t
8
t
cnv
t
acq
t
cyc
t
6
ADS8319
www.ti.com SLAS600A –MAY 2008–REVISED SEPTEMBER 2013
Refer to Figure 55 for the connection diagram. SDI for device 1 is wired to it's CONVST and CONVST for all the
devices in the chain are wired together. SDO of device 1 goes to SDI of device 2 and so on. SDO of the last
device in the chain goes to the digital host. In this mode there is no CS signal. On the rising edge of CONVST,
all of the device in the chain sample the analog input and enter the conversion phase. For the first device, SDI
and CONVST are wired together, and the setup time of SDI to rising edge of CONVST is adjusted so that the
device still enters chain mode even though SDI and CONVST rise together. It is necessary that SCLK is high at
the rising edge of CONVST so that the device generates a busy indicator at the end of the conversion. In this
mode, CONVST continues to be high from the start of the conversion until all of the data bits are read. Once
started, conversion continues irrespective of the state of SCLK.
At the end of the conversion, all the devices in the chain generate busy indicators. On the first falling edge of
SCLK following the busy indicator bit, all of the devices in the chain output their conversion data starting with the
MSB bit. After this the next lower data bit is output on every falling edge of SCLK. While every device outputs its
data on the SDO pin, it also receives the previous device data on the SDI pin (except for device #1) and stores it
in the shift register. Each device latches incoming data on every falling edge of SCLK. SDO of the first device in
the chain goes high after the 17
th
falling edge of SCLK. All subsequent devices in the chain output the stored
data from the pervious device in MSB first format immediately following their own data word. It needs 16 × N + 1
clock pulses to read data for N devices in the chain.
Figure 56. Interface Timing Diagram, Daisy Chain Mode With Busy Indicator
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