Datasheet

CONVST
SDO
SCLK
SDI
CONVST
SDO
SCLK
SDI SDI
CLK
CNV
ADS8319#2
DigitalHost
ADS8319#1
2 3
16
17
SDI (CS)
ACQUISITION
CONVERSION
ACQUISITION
SCLK
SDO
t
5
t
6
t
dis
t
2
t
3
t
clkh
t
clkl
t
clk
1
D15 D14
D1
D0
t
4
CNVST
t
acq
t
cyc
t
cnv
ADS8319
www.ti.com SLAS600A –MAY 2008–REVISED SEPTEMBER 2013
When the conversion is over, the device enters the acquisition phase and powers down, forces SDO out of three
state, and outputs a busy indicator bit (low level). The device outputs the MSB of the data on the first falling edge
of SCLK after the conversion is over and continues to output the next lower data bits on every falling edge of
SCLK. SDO goes to three state after the 17
th
falling edge of SCLK or SDI (CS) high, whichever occurs first.
Care needs to be taken so that CONVST and SDI are not low together at any time during the cycle.
Figure 52. Interface Timing Diagram, 4 Wire CS Mode With Busy Indicator
Daisy Chain Mode
Daisy chain mode is selected if SDI is low at the time of CONVST rising edge. This mode is useful to reduce
wiring and hardware like digital isolators in the applications where multiple (ADC) devices are used. In this mode
all of the devices are connected in a chain (SDO of one device connected to the SDI of the next device) and data
transfer is analogous to a shift register.
Like CS mode even this mode offers operation with or without a busy indicator. The following section discusses
these interface options in detail.
Daisy Chain Mode Without Busy Indicator
Figure 53. Connection Diagram, Daisy Chain Mode Without Busy Indicator (SDI = 0)
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