Datasheet

CONVST
SDO
CNV
CLK
SDI
SDI
ADS8319
DigitalHost
IRQ
+VBD
CS
1 2
15
16
ACQUISITION
CONVERSION ACQUISITION
SCLK
SDO
t
en
t
dis
t
3
t
clkh
t
clkl
t
clk
CONVST
t
en
17
18
D15#1 D14#1
D1#1
D0#1
D15#2 D14#2
D1#2
D0#2
31 32
t
6
t
dis
t
4
t
5
t
acq
t
2
t
cnv
SDI( )#1CS
SDI( )#2CS
ADS8319
SLAS600A –MAY 2008–REVISED SEPTEMBER 2013 www.ti.com
When the conversion is over, the device enters the acquisition phase and powers down. SDI falling edge can
occur after the maximum conversion time (t
cnv
in timing requirements table). Note that it is necessary that SDI is
high at the end of the conversion, so that the device does not generate a busy indicator. The falling edge of SDI
brings SDO out of 3-state and the device outputs the MSB of the data. Subsequent to this the device outputs the
next lower data bits on every falling edge of SCLK. SDO goes to three state after the 16
th
falling edge of SCLK or
SDI (CS) high, whichever occurs first. As shown in Figure 49, it is possible to hook multiple devices on the same
data bus. In this case the second device SDI (acting as CS) can go low after the first device data is read and
device 1 SDO is in three state.
Care needs to be taken so that CONVST and SDI are not low together at any time during the cycle.
Figure 50. Interface Timing Diagram, 4 Wire CS Mode Without Busy Indicator
4 Wire CS Mode With Busy Indicator
Figure 51. Connection Diagram, 4 Wire CS Mode With Busy Indicator
As mentioned before for selecting CS mode it is necessary that SDI is high at the time of the CONVST rising
edge. Unlike in the three wire interface option, SDI is controlled by the digital host and acts like CS. As shown in
Figure 52, SDI goes to a high level before the rising edge of CONVST. The rising edge of CONVST while SDI is
high selects CS mode, forces SDO to three state, samples the input signal, and the device enters the conversion
phase. In the 4 wire interface option CONVST needs to be at a high level from the start of the conversion until all
of the data bits are read. Conversion is done with the internal clock and it continues irrespective of the state of
SDI. As a result it is possible to toggle SDI (acting as CS) to select other devices on the board. But it is
absolutely necessary that SDI is low before the minimum conversion time (t
cnv
in timing requirements table) is
elapsed and continues to stay low until the end of the maximum conversion time. A low level on the SDI input at
the end of a conversion ensures the device generates a busy indicator.
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