Datasheet

CS1
CNV
CS2
SDI
CLK
CONVST SDI
SDO
SCLK
CONVST SDI
SDO
SCLK
ADS8319#1
DigitalHost
ADS8319#2
2 3
16
17
CONVST
ACQUISITION
CONVERSION
ACQUISITION
SCLK
SDO
t
1
t
dis
t
2
t
3
t
clkh
t
clkl
1
D15 D14
D1
D0
t
cyc
t
acq
t
cnv
t
clk
ADS8319
www.ti.com SLAS600A –MAY 2008–REVISED SEPTEMBER 2013
Figure 48. Interface Timing Diagram, 3 Wire CS Mode With Busy Indicator (SDI = 1)
4 Wire CS Mode Without Busy Indicator
Figure 49. Connection Diagram, 4 Wire CS Mode Without Busy Indicator
As mentioned before for selecting CS mode it is necessary that SDI is high at the time of the CONVST rising
edge. Unlike in three wire interface option, SDI is controlled by digital host and acts like CS. As shown in
Figure 50, SDI goes to a high level before the rising edge of CONVST. The rising edge of CONVST while SDI is
high selects CS mode, forces SDO to three state, samples the input signal, and the device enters the conversion
phase. In the 4 wire interface option CONVST needs to be at a high level from the start of the conversion until all
of the data bits are read. Conversion is done with the internal clock and it continues irrespective of the state of
SDI. As a result it is possible to bring SDI (acting as CS) low to select other devices on the board. But it is
absolutely necessary that SDI is high again before the minimum conversion time (t
cnv
in timing requirements
table) is elapsed.
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