Datasheet

CONVST
SCLK
SDO
CNV
CLK
SDI
SDI
ADS8319
DigitalHost
+VBD
ADS8319
www.ti.com SLAS600A –MAY 2008–REVISED SEPTEMBER 2013
DETAILED DESCRIPTIONS AND TIMING DIAGRAMS
The ADS8319 is a high-speed, low power, successive approximation register (SAR) analog-to-digital converter
(ADC) that uses an external reference. The architecture is based on charge redistribution, which inherently
includes a sample/hold function.
The ADS8319 is a single channel device. The analog input is provided to two input pins: +IN and -IN where -IN is
a pseudo differential input and it has a limited range of ±0.1 V. When a conversion is initiated, the differential
input on these pins is sampled on the internal capacitor array. While a conversion is in progress, both +IN and -
IN inputs are disconnected from any internal function.
The ADS8319 has an internal clock that is used to run the conversion, and hence the conversion requires a fixed
amount of time. After a conversion is completed, the device reconnects the sampling capacitors to the +IN and
–IN pins, and the device is in the acquisition phase. During this phase the device is powered down and
conversion data can be read.
The device digital output is available in SPI compatible format. It easily interfaces with microprocessors, DSPs, or
FPGAs.
This is a low pin count device; however, it offers six different options for the interface. They can be grossly
classified as CS mode (3- or 4-wire interface) and daisy chain mode. In both modes it can either be with or
without a busy indicator, where the busy indicator is a bit preceeding the 16-bit serial data.
The 3-wire interface CS mode is useful for applications which need galvanic isolation on-board, where as 4-wire
interface CS mode makes it easy to control an individual device while having multiple devices on-board. The
daisy chain mode is provided to hook multiple devices in a chain like a shift register and is useful to reduce
component count and the number of signal traces on the board.
CS MODE
CS Mode is selected if SDI is high at the rising edge of CONVST. As indicated before there are four different
interface options available in this mode, namely 3-wire CS mode without busy indicator, 3-wire CS mode with
busy indicator, 4-wire CS mode without busy indicator, 4-wire CS mode with busy indicator. The following section
discusses these interface options in detail.
3-Wire CS Mode Without Busy Indicator
Figure 45. Connection Diagram, 3-Wire CS Mode without Busy Indicator (SDI = 1)
The three wire interface option in CS mode is selected if SDI is tied to +VBD (see Figure 45). In the three wire
interface option, CONVST acts like CS. As shown in Figure 46, the device samples the input signal and enters
the conversion phase on the rising edge of CONVST, at the same time SDO goes to 3-state. Conversion is done
with the internal clock and it continues irrespective of the state of CONVST. As a result it is possible to bring
CONVST (acting as CS) low after the start of the conversion to select other devices on the board. But it is
absolutely necessary that CONVST is high again before the minimum conversion time (t
cnv
in timing
requirements table) is elapsed. A high level on CONVST at the end of the conversion ensures the device does
not generate a busy indicator.
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