Datasheet

D
OUT
1.4V
TestPoint
3kW
100pF
C
LOAD
LoadCircuitfort ,t ,andt
dDO r f
VoltageWaveformsforD RiseandFallTimes,t ,t
OUT r f
VoltageWaveformsforD DelayTimes,t
OUT dDO
VoltageWaveformsfort
dis
VoltageWaveformsfort
en
LoadCircuitfort andt
dis en
t
r
D
OUT
90%
10%
t
f
D
OUT
TestPoint
t Waveform2,t
dis en
V
DD
t Waveform1
dis
100pF
C
LOAD
3kW
t
dis
CS/SHDN
D
OUT
Waveform1
(3)
D
OUT
Waveform2
(4)
90%
10%
90%
41
B15
5
t
en
CS/SHDN
DCLOCK
D
OUT
t
dDO
D
OUT
DCLOCK
t
hDO
(3)Waveform1isforanoutputwithinternalconditionssuchthat
theoutputishighunlessdisabledbytheoutputcontrol.
(4)Waveform2isforanoutputwithinternalconditionssuchthat
theoutputislowunlessdisabledbytheoutputcontrol.
CS/SHDN
D
OUT
DCLOCK
t
CYC
PowerDown
ConversionSample
Usepositiveclockedgefordatatransfer
t
SUCS
t
CONV
t
SMPL
NOTE:(1)Aminimumof22clockcyclesarerequiredfor16-bitconversion;24clockcyclesareshown.
If remainslowattheendofconversion,anewdatastreamisshiftedoutwithLSB-firstdatafollowedbyzeroesindefinitely.CS
B15
(MSB)
B14 B13 B12 B11 B10 B9 B8
B0
(1)
(LSB)
B7 B1B6 B2B5 B3B4
Hi-Z
0
Hi-Z
t
CSD
NOTES:
CS/SHDN
D
OUT
DCLOCK
t
CONV
t
SUCS
t
CSD
t
CYC
PowerDown
t
SMPL
NOTE:(2)Aftercompletingthedatatransfer,iffurtherclocksareappliedwith low,theA/Dconverterwilloutputzeroesindefinitely.CS
B15
(MSB)
B14 B6 B5 B4 B4B3 B3B2 B2B1 B1B0
Hi-Z Hi-Z
B5 B0 B11 B12 B13 B14
B15
(2)
(LSB) (MSB)
0
ADS8317
SBAS356D –JUNE 2007–REVISED OCTOBER 2009 .................................................................................................................................................... www.ti.com
TIMING INFORMATION
Figure 1. Timing Diagrams
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