Datasheet

7 Evaluating with the ADCPro Software
7.1 Using the MSOP-8EVM-PDK Plug-In
7.1.1 Continuous Clock—Max SCLK
Evaluating with the ADCPro Software www.ti.com
The evaluation software is based on ADCPro, a program that operates using a variety of plug-ins. (The
MSOP-8EVM plug-in is installed as described in the installation section.)
To use ADCPro, load an EVM plug-in and a test plug-in. To load an EVM plug-in, select it from the EVM
menu. To load a test plug-in, select it from the Test menu. To unload a plug-in, select the Unload option
from the corresponding menu.
Only one of each kind of plug-in can be loaded at a time. If you select a different plug-in, the previous
plug-in is unloaded.
The MSOP-8EVM-PDK plug-ins for ADCPro provide complete control over all settings of the MSOP-8EVM
devices. The MSOP-8EVM device settings can be adjusted when not acquiring data. During acquisition,
all controls are disabled and settings may not be changed.
When you change a setting on the MSOP-8EVM device plug-in, the setting is immediately updated on the
board.
If you unload and reload the plug-in, the software will attempt to load settings from the board.
Settings on the MSOP-8EVM device correspond to the settings described in the particular installed device
data sheet. For example, if the installed MSOP-8EVM device is the ADS8326, see the ADS8326 data
sheet (available for download at www.ti.com) for details.
The user-configurable settings include Sample Rate, Vref and Mode. The sample rate can only be set up
to the maximum stipulated sample rate in the device data sheet (that is, 250kHz for the ADS8326) and
Vref is specified in the device data sheet (that is, 0.1V to 5V for the ADS8326). The three available clock
modes are Continuous Clock—Max SCLK, Clockstop Mode—Max SCLK, and Continuous
Mode—Stretched SCLK.
In this mode, SCLK frequency is given as the highest possible serial clock frequency for the data
converter under test. The sampling frequency can be adjusted to any desired rate by entering a value in
the sampling rate window. The software associated with the MSOP-8 plugin adjusts the number of clock
cycles between rising CS pulses to accommodate the requested sampling rate while keeping the serial
clock speed constant.
Figure 14. Continuous Clock—Max SCLK
MSOP-8EVM and MSOP-8EVM-PDK18 SBAU140 – December 2008
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