Datasheet

ADS823, ADS826
SBAS070B
4
www.ti.com
TIMING DIAGRAM
SYMBOL DESCRIPTION MIN TYP MAX UNITS
t
CONV
Convert Clock Period 16.6 100µsns
t
L
Clock Pulse LOW 7.9 8.3 ns
t
H
Clock Pulse HIGH 7.9 8.3 ns
t
D
Aperture Delay 3 ns
t
1
Data Hold Time, C
L
= 0pF 3.9 ns
t
2
New Data Delay Time, C
L
= 15pF max 12 ns
5 Clock Cycles
Data Invalid
t
D
t
L
t
H
t
CONV
N – 5N – 4N – 3N – 2N – 1 N N + 1 N + 2
Data Out
Clock
Analog In
N
t
2
N + 1
N + 2
N + 3
N + 4
N + 5
N + 6
N + 7
t
1
Top View SSOP
PIN CONFIGURATION
PIN DESIGNATOR DESCRIPTION
1 GND Ground
2 Bit 1 Data Bit 1 (D9) (MSB)
3 Bit 2 Data Bit 2 (D8)
4 Bit 3 Data Bit 3 (D7)
5 Bit 4 Data Bit 4 (D6)
6 Bit 5 Data Bit 5 (D5)
7 Bit 6 Data Bit 6 (D4)
8 Bit 7 Data Bit 7 (D3)
9 Bit 8 Data Bit 8 (D2)
10 Bit 9 Data Bit 9 (D1)
11 Bit 10 Data Bit 10 (D0) (LSB)
12 OE Output Enable. HI: High Impedance State.
LO: Normal Operation (Internal Pull-Down
Resistor)
13 PD Power Down: HI = Power Down; LO = Normal
14 CLK Convert Clock Input
15 +V
S
+5V Supply
16 GND Ground
17 RSEL Input Range Select: HI = 2V; LO = 1V
18 INT/EXT Reference Select: HI = External; LO = Internal
19 REFB Bottom Reference
20 ByB Bottom Ladder Bypass
21 ByT Top Ladder Bypass
22 REFT Top Reference
23 CM Common-Mode Voltage Output
24 IN Complementary Input (–)
25 IN Analog Input (+)
26 GND Ground
27 +V
S
+5V Supply
28 VDRV Output Logic Driver Supply Voltage
PIN DESCRIPTIONS
GND
Bit 1 (MSB)
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 8
Bit 9
Bit 10 (LSB)
OE
PD
CLK
VDRV
+V
S
GND
IN
IN
CM
REFT
ByT
ByB
REFB
INT/EXT
RSEL
GND
+V
S
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
ADS823
ADS826