Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsData collecting ICsData acquisition IC - AD converter (ADC) External , Internal SSOP 28

10-Bit, 40MHz Sampling

ANALOG-TO-DIGITAL CONVERTERS

FEATURES

● HIGH SNR: 60dB

● HIGH SFDR: 72dBFS

● LOW POWER: 190mW

● INTERNAL/EXTERNAL REFERENCE OPTION

● SINGLE-ENDED OR

FULLY DIFFERENTIAL ANALOG INPUT

● PROGRAMMABLE INPUT RANGE

● LOW DNL: 0.5LSB

● SINGLE +5V SUPPLY OPERATION

●

+3V OR +5V LOGIC I/O COMPATIBLE (ADS825)

● POWER DOWN: 20mW

● SSOP-28 PACKAGE

APPLICATIONS

● MEDICAL IMAGING

● TEST EQUIPMENT

● COMPUTER SCANNERS

● COMMUNICATIONS

● VIDEO DIGITIZING

DESCRIPTION

The ADS822 and ADS825 are pipeline, CMOS Analog-to-Digital

Converters (ADC) that operate from a single +5V power supply.

These converters provide excellent performance with a single-ended

input and can be operated with a differential input for added spurious

performance. These high-performance converters include a 10-bit

quantizer, high-bandwidth track-and-hold, and a high-accuracy inter-

nal reference. They also allow for the user to disable the internal

reference and utilize external references. This external reference

option provides excellent gain and offset matching when used in

multichannel applications, or in applications where full-scale range

adjustment is required.

10-Bit

Pipelined

A/D Core

Internal

Reference

Optional External

Reference

Timing

Circuitry

Error

Correction

Logic

3-State

Outputs

T/H

CLK VDRV

ADS822

ADS825

OEPDInt/Ext

•

INV

825

ADS822

ADS825

SBAS069B – MARCH 2001 – REVISED AUGUST 2002

www.ti.com

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

The ADS822 and ADS825 employ digital error correction techniques

to provide excellent differential linearity for demanding imaging appli-

cations. Its low distortion and high SNR give the extra margin needed

for medical imaging, communications, video, and test instrumentation.

The ADS822 and ADS825 offer power dissipation of 190mW and also

provide a power-down mode, thus reducing power dissipation to only

20mW. The ADS825 is +3V or +5V logic I/O compatible.

The ADS822 and ADS825 are specified at a maximum sampling

frequency of 40MSPS and a single-ended input range of 1.5V to 3.5V.

The ADS822 and ADS825 are available in an SSOP-28 package and

are pin-for-pin compatible with the 10-bit, 60MSPS ADS823 and

ADS826, and the 10-bit, 75MSPS ADS828, providing an upgrade

path to higher sampling frequencies.

Summary of content (18 pages)

PAGE 1
ADS A DS ADS822 ADS825 825 82 2 SBAS069B – MARCH 2001 – REVISED AUGUST 2002 10-Bit, 40MHz Sampling ANALOG-TO-DIGITAL CONVERTERS ● +3V OR +5V LOGIC I/O COMPATIBLE (ADS825) ● POWER DOWN: 20mW ● SSOP-28 PACKAGE FEATURES ● ● ● ● ● HIGH SNR: 60dB HIGH SFDR: 72dBFS LOW POWER: 190mW INTERNAL/EXTERNAL REFERENCE OPTION SINGLE-ENDED OR FULLY DIFFERENTIAL ANALOG INPUT ● PROGRAMMABLE INPUT RANGE ● LOW DNL: 0.
PAGE 2
ABSOLUTE MAXIMUM RATINGS(1) ELECTROSTATIC DISCHARGE SENSITIVITY +VS ....................................................................................................... +6V Analog Input ............................................................. –0.3V to (+VS + 0.3V) Logic Input ............................................................... –0.3V to (+VS + 0.3V) Case Temperature ......................................................................... +100°C Junction Temperature ....................
PAGE 3
ELECTRICAL CHARACTERISTICS (Cont.) At TA = full specified temperature range, VS = +5V, single-ended input range = 1.5V to 3.5V, and sampling rate = 40MHz, external reference, unless otherwise noted.
PAGE 4
PIN DESCRIPTIONS PIN CONFIGURATION Top View SSOP GND 1 28 VDRV Bit 1 (MSB) 2 27 +VS Bit 2 3 26 GND Bit 3 4 25 IN Bit 4 5 24 IN Bit 5 6 23 CM Bit 6 7 22 REFT Bit 7 8 21 ByT Bit 8 9 20 ByB Bit 9 10 19 REFB Bit 10 (LSB) 11 18 INT/EXT OE 12 17 RSEL PD 13 16 GND CLK 14 15 +VS ADS822 ADS825 PIN DESIGNATOR 1 2 3 4 5 6 7 8 9 10 11 12 GND Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 8 Bit 9 Bit 10 OE 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 PD CLK +
PAGE 5
ELECTRICAL CHARACTERISTICS At TA = full specified temperature range, VS = +5V, single-ended input range = 1.5V to 3.5V, sampling rate = 40MHz, and external reference, unless otherwise noted.
PAGE 6
ELECTRICAL CHARACTERISTICS (Cont.) At TA = full specified temperature range, VS = +5V, single-ended input range = 1.5V to 3.5V, sampling rate = 40MHz, and external reference, unless otherwise noted. UNDERSAMPLING (Differential Input, 2Vp-p) 2-TONE INTERMODULATION DISTORTION 0 0 fS = 40MHz fIN = 75MHz SNR = 59dBFS SFDR = 66dBFS –20 Magnitude (dB) Magnitude (dB) –20 f1 = 9.5MHz at –7dBFS f2 = 9.9MHz at –7dBFS IMD (3) = –67dB –40 –60 –40 –60 –80 –80 –100 –100 0 5 10 15 0 20 5 10 1.
PAGE 7
ELECTRICAL CHARACTERISTICS (Cont.) At TA = full specified temperature range, VS = +5V, single-ended input range = 1.5V to 3.5V, sampling rate = 40MHz, and external reference, unless otherwise noted. DYNAMIC PERFORMANCE vs TEMPERATURE DYNAMIC PERFORMANCE vs INPUT FREQUENCY 75 75 SFDR SFDR, SNR (dBFS) SFDR, SNR (dBFS) 70 65 60 SNR 55 70 SFDR (fIN = 10MHz) 65 SFDR (fIN = 20MHz) SNR (fIN = 10MHz) 60 SNR (fIN = 20MHz) 55 50 0.
PAGE 8
APPLICATION INFORMATION THEORY OF OPERATION The ADS822 and ADS825 are high-speed CMOS ADCs which employ a pipelined converter architecture consisting of nine internal stages. Each stage feeds its data into the digital error correction logic ensuring excellent differential linearity and no missing codes at the 10-bit level. The output data becomes valid on the rising clock edge (see Timing Diagram). The pipeline architecture results in a data latency of 5 clock cycles.
PAGE 9
1.62kΩ +5V VCM +2.5V 1.62kΩ +5V 0.1µF 50Ω REFB +1.5V RS 50Ω VIN REFT +3.5V RSEL +VS IN OPA690 10pF +VIN 0V ADS822 ADS825 RF 402Ω –VIN CM IN RG 402Ω 0.1µF INT/EXT 0.1µF GND FIGURE 2. AC-Coupled Input Configuration for a 2Vp-p Full-Scale Range and a Common-Mode Voltage, VCM, at +2.5V Derived From the Internal Top (REFT) and Bottom References (REFB). +5V 1.62kΩ +5V RS 24.9Ω VIN REFT +3.5V 0.1µF RSEL +VS IN OPA642 100pF ADS822 ADS825 –5V RF 402Ω 1.62kΩ CM IN RG 402Ω 0.
PAGE 10
+5V RF 499Ω RIN 499Ω A1 VIN 1/2 OPA2691 +VS RSEL RS 50Ω IN 2Vp-p 10pF ADS822 ADS825 NOTE: RF = RIN, G = –1 CM (+2.5) IN +5V R2 200Ω VCM = +1.25V A2 0.1µF REFB (+1.5V) REFT (+3.5V) INT/EXT 50Ω 0.1µF 1/2 OPA2691 0.1µF R1 1kΩ RF 1kΩ FIGURE 4. DC-Coupled Interface Circuit with Dual Current-Feedback Amplifier OPA2681.
PAGE 11
resistive reference ladder. The bandgap reference circuit includes logic functions that allows setting the analog input swing of the ADS822 and ADS825 to either a 1Vp-p or 2Vp-p full-scale range simply by tying the RSEL pin to a Low or High potential, respectively. While operating the ADS822 in the external reference mode, the buffer amplifiers for the REFT and REFB are disconnected from the reference ladder.
PAGE 12
the following equation. If this value is near your system requirements, input clock jitter must be reduced. Jitter SNR = 20 log 1 rms signal to rms noise 2π ƒIN t A where: ƒIN is input signal frequency tA is rms clock jitter Particularly in undersampling applications, special consideration should be given to clock jitter. The clock input should be treated as an analog input in order to achieve the highest level of performance.
PAGE 13
PACKAGE OPTION ADDENDUM www.ti.
PAGE 14
PACKAGE OPTION ADDENDUM www.ti.com (4) 31-May-2013 There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device.
PAGE 15
PACKAGE MATERIALS INFORMATION www.ti.com 30-May-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant ADS822E/1K SSOP DB 28 1000 330.0 16.4 8.1 10.4 2.5 12.0 16.0 Q1 ADS825E/1K SSOP DB 28 1000 330.0 16.4 8.1 10.4 2.5 12.0 16.
PAGE 16
PACKAGE MATERIALS INFORMATION www.ti.com 30-May-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADS822E/1K SSOP DB 28 1000 367.0 367.0 38.0 ADS825E/1K SSOP DB 28 1000 367.0 367.0 38.
PAGE 17
MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0°–ā8° 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters.
PAGE 18
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