Datasheet

ADS807
5
SBAS072A
www.ti.com
TIMING DIAGRAM
6 Clock Cycles
Data Invalid
t
D
t
L
t
H
t
CONV
N – 6N – 5N – 4N – 3N – 2N – 1 N N + 1
Data Out
Clock
Analog In
N
t
2
N + 1
N + 2
N + 3
N + 4
N + 5
N + 6
N + 7
t
1
SYMBOL DESCRIPTION MIN TYP MAX UNITS
t
CONV
Convert Clock Period 18.87 100µsns
t
L
Clock Pulse LOW 9.4 t
CONV
/2 ns
t
H
Clock Pulse HIGH 9.4 t
CONV
/2 ns
t
D
Aperture Delay 2 ns
t
1
(1)
Data Hold Time, C
L
= 0pF 2.7 ns
t
2
(1)
New Data Delay Time, C
L
= 15pF max 12 ns
NOTE: (1) t
1
and t
2
times are valid for VDRV voltages of +2.7V to +5V.