Datasheet

CS
DOUT
DIN
t
SU_CSCK
SCLK
ADD3
WRITE REPEAT AIN0 AIN1 AIN2 AIN3 EXT_REF STANDBYTMP_AVG
ADD2
6
ADD1 ADD0 DB11 DB10 DB2 DB1 DB0
t
PH_CSZ
t
CONV
t
DV_CSDO
3-State
54321 13
t
PH_SCLK
t
SCLK
t
D_CKDO
t
HT_CKDO
t
HT_CKDI
t
SU_CKDI
14 15 16
3-State
t
PL_SCLK
t
DZ_CKDO
t
ACQ
ADS8028
SBAS549B –MAY 2011–REVISED MARCH 2012 www.ti.com
PARAMETER MEASUREMENT INFORMATION
TIMING CHARACTERISTICS
Figure 1. Serial Interface Timing Diagram
Timing Requirements for Figure 1
(1)
ADS8028
PARAMETER DESCRIPTION TEST CONDITIONS MIN TYP MAX UNIT
f
SCLK
External serial clock frequency 20 MHz
t
SCLK
External interface clock time period 50 ns
t
PH_SCLK
SCLK high pulse width 0.4 t
SCLK
0.6 t
SCLK
ns
t
PL_SCLK
SCLK low pulse width 0.4 t
SCLK
0.6 t
SCLK
ns
Conversion time: t
SU_CSCK
+ 13 t
SCLK
ns
t
CONV
For channels AIN0 to AIN7 f
SCLK
= 20 MHz 700 ns
For internal temperature sensor measurement 100 µs
t
PH_CSZ
CS high pulse width 6 ns
t
ACQ
Acquisition time (for channel AINx) f
SCLK
= 20 MHz 100 ns
t
SU_CSCK
Setup time: CS to SCLK falling edge 10 ns
t
DV_CSDO
Delay time between CS falling edge to DOUT enabled 17 ns
DVDD = 1.65 V to 3 V 32 ns
Delay time between SCLK falling edge to (new) data
t
D_CKDO
DVDD = 3 V to 3.6 V 29 ns
available on DOUT
DVDD = 3.6 V to 5.25 V 28 ns
Hold time: SCLK falling edge to (previous) data valid on
t
HT_CKDO
10 ns
DOUT
Delay time between 16th SCLK falling edge to DOUT
t
DZ_CKDO
12 27 ns
going to high-impedance
Delay time between CS going high to DOUT going to high-
t
DZ_CSDO
26 ns
impedance
t
SU_CKDI
DIN setup time before SCLK falling edge 5 ns
t
HT_CKDI
DIN hold time after SCLK falling edge 4 ns
t
ACQ_TMP
TM_BUSY falling edge to CS falling edge 100 ns
t
PU_STANDBY
Power-up time after coming out of STANDBY mode 1 µs
Internal reference mode,
t
POWER_UP
Power-up time after coming out of power-down mode 6 ms
10-µF capacitor on REF pin
(1) Specifications apply from T
A
= –40°C to +125°C, AVDD = 2.7 V to 3.6 V, DVDD = 1.65 V to 5.25 V, V
REF
= 2.5 V internal, load on
DOUT = 15 pF || 100 kΩ, and t
R
= t
F
= 5 ns (10% to 90% of DVDD) and timed from a voltage level of 0.5 DVDD, unless otherwise
noted.
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