Datasheet

MXO AINP

Ch0

Chn*

Ch2

Ch1

ADC

HighInput

impedancePGA

(ornoninvertingbuffer

like THS4031)

GPIO

1,2,3

PGA Gain

Control

GPIO0

H/L Alarm

SDI

SCLK

SDO

Host

REF

10 Fm

REF5025

o/p

Fromsensors,INA etc.

Sourceimpedancehasvery

littleeffectonperformance.

Referto TypicalCharacteristics

fordetails.

ADS7950, ADS7951, ADS7952, ADS7953

ADS7954, ADS7955, ADS7956, ADS7957

ADS7958, ADS7959, ADS7960, ADS7961

www.ti.com

SLAS605A –JUNE 2008–REVISED JANUARY 2010

GPIO 1 to 3 are available only in TSSOP packaged devices. QFN device offers 'GPIO 0' only. As a result all

references related to 'GPIO 0' only are valid in case of QFN package devices.

Figure 58. Typical Application Diagram Showing Common Buffer/PGA for all Channels

When the converter samples an input, the voltage difference between AINP and AGND is captured on the

internal capacitor array. The (peak) input current through the analog inputs depends upon a number of factors:

sample rate, input voltage, and source impedance. The current into the ADS79XX charges the internal capacitor

array during the sample period. After this capacitance has been fully charged, there is no further input current.

When the converter goes into hold mode, the input impedance is greater than 1 GΩ.

Care must be taken regarding the absolute analog input voltage. To maintain linearity of the converter, the Ch0 ..

Chn and AINP inputs should be within the limits specified. Outside of these ranges, converter linearity may not

meet specifications.

Product Folder Link(s): ADS7950, ADS7951, ADS7952, ADS7953 ADS7954, ADS7955, ADS7956, ADS7957 ADS7958,

ADS7959, ADS7960, ADS7961