Datasheet

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
16
SCLK
CS
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
SDO
t
SU1
t
D1
t
H1
t
D2
t
D3
Sample
N
Sample
N+1
t
ACQ
t
CONV
1/f
SAMPLE
DatafromSampleN-1
t
W1
t
WH
t
WL
t
D4
ADS7947
ADS7948
ADS7949
www.ti.com SLAS708 –SEPTEMBER 2010
TIMING DIAGRAM
TIMING REQUIREMENTS
All specifications at DVDD = 1.65V to AVDD and T
A
= –40°C to +125°C, unless otherwise noted.
PARAMETER TEST CONDITIONS
(1)
MIN TYP MAX UNIT
ADS7947 (12-bit) 13.5 SCLK
t
CONV
Conversion time ADS7948 (10-bit) 10.5 SCLK
ADS7949 (8-bit) 8.5 SCLK
t
ACQ
Acquisition time 80 ns
SCLK = 34MHz,
f
SAMPLE
Sample rate (throughput rate) 2 MSPS
16 clock frame
ADS7947 (12-bit) SCLK = 34MHz 2.1 MSPS
f
SAMPLE MAX
= 1/( t
CONV MAX
+ t
ACQ MIN
) ADS7948 (10-bit) SCLK = 34MHz 2.57 MSPS
ADS7949 (8-bit) SCLK = 34MHz 3 MSPS
t
W1
Pulse width CS high 25 ns
DVDD = 1.8V 14.5 ns
t
D1
Delay time, CS low to first data (D0-15) out DVDD = 3V 12.5 ns
DVDD = 5V 8.5 ns
DVDD = 1.8V 3.5 ns
t
SU1
Setup time, CS low to first rising edge of SCLK DVDD = 3V 3.5 ns
DVDD = 5V 3.5 ns
DVDD = 1.8V 11 ns
t
D2
(2)
Delay time, SCLK falling to SDO DVDD = 3V 9 ns
DVDD = 5V 7.1 ns
DVDD = 1.8V 4 ns
t
H1
Hold time, SCLK falling to data valid DVDD = 3V 3 ns
DVDD = 5V 2 ns
DVDD = 1.8V 15 ns
t
D3
Delay time, CS high to SDO 3-state DVDD = 3V 12.5 ns
DVDD = 5V 8.5 ns
Delay time CS rising edge from conversion end 10
t
D4
ns
(refer to the t
CONV
specification for conversion time)
t
WH
Pulse duration, SCLK high 11 ns
t
W1
Pulse duration, SCLK low 11 ns
SCLK frequency 0.4 34 40 MHz
t
PDSU
Setup time, PDEN high to CS rising edge 2
ns
(refer to Figure 50 and Figure 51)
t
PDH
Hold time, CS rising edge to PDEN falling edge (refer to Figure 50) 20 ns
(1) 1.8V specifications apply from 1.65V to 2V; 3V specifications apply form 2.7V to 3.6V; 5V specifications apply from 4.75V to 5.25V.
(2) With 50pF load.
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