Datasheet

AVDD
DVDD
CHSEL
SCLK
SDO
CS
4 3 2 1
5
6
7
8
9 10 11 12
16
15
14
13
PDEN
NC
GND REF REFGND
AIN0P
AIN1P
AIN0N
AIN1N
NC
470pF
C
2
470pF
C
1
5W
Input
Signal
1 Fm
C
3
Common Analog/
DigitalGroundPlane
Reference
Input
Analog
Supply
1 Fm
C
4
47W
R
1
0.1 Fm
C
5
1 Fm
C
6
Digital
Supply
DigitalSignalsfromHost
ADS7947
ADS7948
ADS7949
U0
5W
5W
5W
Input
Signal
ADS7947
ADS7948
ADS7949
www.ti.com SLAS708 –SEPTEMBER 2010
The device sampling rate can be maximized by using a 34MHz clock even for lower throughputs. Table 2 shows
typical calculations for the ADS7947(12-bit).
Table 2. Sampling Frequency versus Source Impedance for the ADS7947 (12-Bit)
SAMPLING TIME, CONVERSION TIME, CYCLE TIME, t
ACQ
+ SAMPLING RATE
R
SOURCE
(Ω) C
BYPASS
(pF) t
ACQ
(ns) t
CONV
(ns) t
CONV
(ns) (MSPS)
397
180 10 80 477 2
(with 34MHz clock)
397
250 10 107 504 1.98
(with 34MHz clock)
397
1000 10 422 819 1.2
(with 34MHz clock)
397
5000 10 2102 2499 0.4
(with 34MHz clock)
It is necessary to allow 1000ns additional sampling time over what is shown in Table 2 if PDEN (pin 12) is set
high.
PCB LAYOUT/SCHEMATIC GUIDELINES
ADCs are mixed-signal devices. For maximum performance, proper decoupling, grounding, and proper
termination of digital signals is essential. Figure 54 shows the essential components around the ADC. All
capacitors shown are ceramic. These decoupling capacitors must be placed close to the respective signal pins.
There is a 47Ω source series termination resistor shown on the SDO signal. This resistor must be placed as
close to pin 15 as possible. Series terminations for SCLK and CS must be placed close to the host.
Figure 54. Recommended ADC Schematic
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Product Folder Link(s): ADS7947 ADS7948 ADS7949