Datasheet

OPA365
+
-
47 F0p
ADS7947
ADS7948
ADS7949
AINxN
AINxP
+VA
0VtoV
REF
5W
AVDD
50W
5W
GND
SamplingTime
SettlingResolution ln(2)´
FilterTimeConstant(t )=
AU
FilterTimeConstant(t )=R C´
AU
1
2 t´ p ´
AU
FilterBandwidth=
ADS7947
ADS7948
ADS7949
www.ti.com SLAS708 –SEPTEMBER 2010
APPLICATION INFORMATION
The device employs a sample-and-hold stage at the input; see Figure 39 for a typical equivalent circuit of a
sample-and-hold stage. The device connects a 32pF sampling capacitor during sampling. This configuration
results in a glitch at the input terminals of the device at the start of the sample. The external circuit must be
designed in such a way that the input can settle to the required accuracy during the sampling time chosen.
Figure 52 shows a typical driving circuit for the analog inputs.
Figure 52. Typical Input Driving Circuit
The 470pF capacitor across the AINxP and AINxN terminals decouples the driving op amp from the sampling
glitch. It is recommended to split the series resistance of the input filter in two equal values as shown in
Figure 52. It is recommended that both input terminals see the same impedance from the external circuit. The
low-pass filter at the input limits noise bandwidth of the driving op amp. Select the filter bandwidth so that the
full-scale step at the input can settle to the required accuracy during the sampling time. Equation 1, Equation 2,
and Equation 3 are useful for filter component selection.
Where:
Settling resolution is the accuracy in LSB to which the input needs to settle. A typical settling resolution
for the 12-bit device is 13 or 14. (1)
(2)
(3)
Also, make sure the driving op amp bandwidth does not limit the signal bandwidth below filter bandwidth. In
many applications, signal bandwidth may be much lower than filter bandwidth. In this case, an additional
low-pass filter may be used at the input of the driving op amp. This signal filter bandwidth can be selected in
accordance with the input signal bandwidth.
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