Datasheet

1
2
15 16 1
2
15 16 1
2
11
12 13 14
15 16
t
PDSU
t
PDH
Sample
N 1-
Sample
N
Dummy
Sample
DatafromSample
N 2-
DatafromSample
N 1-
DatafromSample
N
SCLK
CS
SDO
Power-Down
State
(Internal)
PDEN
Active Power-Down
1
2
15 16 1
2
15
16 1
2
t
PDSU
Sample
N+1
Sample
N+2
InvalidData
SCLK
CS
SDO
Power-Down
State
(Internal)
PDEN
Sample
N+3
DatafromSample
N+1
DatafromSample
N+2
t
ACQ
(min)+1 sm
ActivePower-Down
ADS7947
ADS7948
ADS7949
SLAS708 –SEPTEMBER 2010 www.ti.com
Figure 50. Entry Into Power-Down with 16-Clock Burst Mode
As shown in Figure 50, the two frames capturing the N–1 and Nth samples are normal 16-clock frames. Keeping
PDEN = 1 prior to the CS rising edge in the next frame ensures that the devices detect the power-down mode.
Data from the Nth sample are read during this frame. It is expected that the Nth sample represents the last data
of interest in the burst of conversions. The devices enter power-down state after the end of conversions. This is
the 14th, 11th, or ninth SCLK rising edge for the 12-, 10-, and 8-bit devices, respectively. The clock may be
stopped after the 14th SCLK falling edge; however, it is recommended to stop the clock after the 16th SCLK
falling edge. Note that it is mandatory not to have more than 29 SCLK falling edges during the CS low period.
This limitation ensures that the devices remain in 16-clock mode.
Figure 51. Exit From Power-Down with 16-Clock Burst Mode
The devices remain in a power-down state as long as CS is low. A CS rising edge with PDEN = 0 brings the
devices out of the power-down state. It is necessary to ensure that the CS high time for the first sample after
power up is more than 1µs + t
ACQ
(min).
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