Datasheet

1 2 14 15 16 17
28
29
30
31 32
SCLK
CS
D2 D1 D0
SDO
t
ACQ
t
CONV
DatafromSampleN
D11 D10
27
18
Power-Down
State
(Internal)
I
DYNAMIC
I
PD-DYNAMIC
I
PD-STATIC
PD-DYNAMIC
if
SCLKisoff;
otherwise,
I .
11thand9thSCLKrisingedgefor10-and8-bitdevices,respectively.
I
AVDD
Profile
t
ACQ
(min)+1 sm
I
STATIC
Active Power-Down Active
ADS7947
ADS7948
ADS7949
www.ti.com SLAS708 –SEPTEMBER 2010
CS can be held low past the 16th falling edge of SCLK. The device continues to output recently converted data
starting with the 16th SCLK falling edge. If CS is held low until the 30th SCLK falling edge, then the device
detects 32-clock mode. Note that the device data from recent conversions are already out with no latency before
the 30th SCLK falling edge. Once 32-clock mode is detected, the device outputs 16 zeros during the next
conversion (in fact, for the first 16 clocks), unlike 16-clock mode where the device outputs the previous
conversion result. SCLK can be stopped after the device has seen the 30th falling edge with CS low.
POWER-DOWN
The ADS7947/8/9 family of devices offer an easy-to-use power-down feature available through a dedicated
PDEN pin (pin 12). A high level on PDEN at the CS rising edge enables the power-down mode for that particular
cycle. Figure 49 to Figure 51 illustrate device operation with power-down in both 32-clock and 16-clock mode.
Many applications must slow device operation. For speeds below approximately 500kSPS, it is convenient to use
32-clock mode with power-down. This results in considerable power savings.
As shown in Figure 49, PDEN is held at a logic '1' level. Note that the device looks at the PDEN status only at
the CS rising edge; however, for continuous low-speed operation, it is convenient to continuously hold PDEN = 1.
The devices detect power-down mode on the CS rising edge with PDEN = 1.
Figure 49. Operation with a 32-Clock Frame in Power-Down Mode (PDEN = 1)
On the CS falling edge, the devices start normal operation as previously described. The devices complete
conversions on the 14th SCLK rising edge. (Conversions complete on the 11th and ninth SCLK rising edge for
10-bit and 8-bit devices, respectively.) The devices enter the power-down state immediately after conversions
complete. However, the devices can still output data as per the timings described previously. The devices
consume dynamic power-down current (I
PD-DYNAMIC
) during data out operations. It is recommended to stop the
clock after the 32nd SCLK falling edge to further save power down to the static power-down current level
(I
PD-STATIC
). The devices power up again on the SCLK rising edge. However, they require an extra 1µs to power
up completely. CS must be high for the 1µs + t
ACQ
(min) period.
In some applications, data collection is accomplished in burst mode. The system powers down after data
collection. 16-clock mode is convenient for these applications. Figure 50 and Figure 51 detail power saving in
16-clock burst mode.
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