Datasheet

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
16
SCLK
CS
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
SDO
Sample
N
Sample
N+1
t
ACQ
t
CONV
DatafromSampleN-1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
16
SCLK
CS
D7 D6 D5 D4 D3 D2 D1 D0
SDO
Sample
N
Sample
N+1
t
ACQ
t
CONV
DatafromSampleN-1
ADS7947
ADS7948
ADS7949
www.ti.com SLAS708 –SEPTEMBER 2010
Figure 44 and Figure 45 show the 16-clock mode operation for the ADS7948 and ADS7949, respectively. The
operation for these 10-bit and 8-bit devices is identical to the ADS7947 except that the conversion ends on
different edges of SCLK. For the ADS7948, the conversion ends and acquisition starts on the 11th SCLK rising
edge. For the ADS7949, the device uses the ninth SCLK rising edge for the conversion end and acquisition start.
Similar to the ADS7947, CS can go high and SCLK may be stopped once the device enters acquisition.
Figure 44. ADS7948 Operating in 16-Clock Mode without Power-Down (PDEN = 0)
Figure 45. ADS7949 Operating in 16-Clock Mode without Power-Down (PDEN = 0)
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Product Folder Link(s): ADS7947 ADS7948 ADS7949