Datasheet

GND
AVDD
REF
REFGND
PDEN
CHSEL
NC
NC
1
2
3
4
12
11
10
9
DVDD
16
AIN0P
5
15 14 13
6 7 8
SDO
AIN0N
SCLK
AIN1N
CS
AIN1P
ADS7947
ADS7948
ADS7949
SLAS708 –SEPTEMBER 2010 www.ti.com
PIN CONFIGURATION
RTE PACKAGE
QFN-16
(TOP VIEW)
PIN FUNCTIONS
PIN NO. PIN NAME FUNCTION DESCRIPTION
1 GND Analog/digital Power supply ground; all analog and digital signals are referred with respect to this pin
2 AVDD Analog ADC power supply
3 REF Analog ADC positive reference input; decouple this pin with REFGND
4 REFGND Analog Reference return; short to analog ground plane
5 AIN0P Analog input Positive analog input, channel 0
Negative analog input, channel 0. Note that the allowable signal swing on this pin is
6 AIN0N Analog input
±0.2V; this pin can be grounded.
Negative analog input, channel 1. Note that the allowable signal swing on this pin is
7 AIN1N Analog input
±0.2V; this pin can be grounded.
8 AIN1P Analog input Positive analog input, channel 1
9 NC — Not connected internally, it is recommended to externally short this pin to GND
10 NC — Not connected internally, it is recommended to externally short this pin to GND
This pin selects the analog input channel.
Low = channel 0, high = channel 1.
11 CH SEL Digital input It is recommended to change the channel within a window of one clock; from half a clock
after the CS falling edge. This change ensures the settling on the multiplexer output
before the sample start.
12 PDEN Digital input This pin enables a power-down feature if it is high at the CS rising edge
13 CS Digital input Chip select signal; active low
14 SCLK Digital input Serial SPI clock
15 SDO Digital output Serial data out
16 DVDD Digital Digital I/O supply
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