Datasheet

0 - V
REF
+
50 Ω
5 Ω
470 pF
5 Ω
OPA836
ADS7946
AINxP
AINxGND
AVDD
GND
+VA
SamplingTime
SettlingResolution ln(2)´
FilterTimeConstant(t )=
AU
FilterTimeConstant(t )=R C´
AU
1
2 t´ p ´
AU
FilterBandwidth=
ADS7945
ADS7946
SBAS539B –JUNE 2011– REVISED SEPTEMBER 2011 www.ti.com
APPLICATION INFORMATION: ADS7946
The ADS7946 employs a sample-and-hold stage at the input; see Figure 76 for a typical equivalent circuit of a
sample-and-hold stage. The device connects a 32 pF sampling capacitor during sampling. This configuration
results in a glitch at the input terminals of the device at the start of the sample. The external circuit must be
designed in such a way that the input can settle to the required accuracy during the sampling time chosen.
Figure 88 shows a typical driving circuit for the analog inputs.
Figure 88. Typical Input Driving Circuit For the ADS7946
The 470 pF capacitor across the AINx and AINxGND terminals decouples the driving op amp from the sampling
glitch. It is recommended to split the series resistance of the input filter in two equal values, as shown in
Figure 88. It is recommended that both input terminals see the same impedance from the external circuit. The
low-pass filter at the input limits noise bandwidth of the driving op amp. Select the filter bandwidth so that the
full-scale step at the input can settle to the required accuracy during the sampling time. Equation 6, Equation 7,
and Equation 8 are useful for filter component selection.
where:
Settling resolution is the accuracy in LSB to which the input must settle. A typical settling resolution for
the 14-bit device is 15 or 16. (6)
(7)
(8)
Also, make sure the driving op amp bandwidth does not limit the signal bandwidth below filter bandwidth. In
many applications, signal bandwidth may be much lower than filter bandwidth. In this case, an additional
low-pass filter may be used at the input of the driving op amp. This signal filter bandwidth can be selected in
accordance with the input signal bandwidth.
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