Datasheet

0 - V
REF
V
REF
- 0
±V
REF
, with
V
REF/2
Common-Mode
+
50 Ω
5 Ω
470 pF
+
50 Ω
5 Ω
OPA836
OPA836
ADS7945
AINxP
AINxN
AVDD
GND
+VA
SamplingTime
SettlingResolution ln(2)´
FilterTimeConstant(t )=
AU
FilterTimeConstant(t )=R C´
AU
1
2 t´ p ´
AU
FilterBandwidth=
ADS7945
ADS7946
www.ti.com SBAS539B –JUNE 2011– REVISED SEPTEMBER 2011
APPLICATION INFORMATION: ADS7945
The ADS7945 employs a sample-and-hold stage at the input; see Figure 76 for a typical equivalent circuit of a
sample-and-hold stage. The device connects a 32 pF sampling capacitor during sampling. This configuration
results in a glitch at the input terminals of the device at the start of the sample. The external circuit must be
designed in such a way that the input can settle to the required accuracy during the sampling time chosen.
Figure 86 shows a typical driving circuit for the analog inputs.
Figure 86. Typical Input Driving Circuit for the ADS7945
The 470 pF capacitor across the AINxP and AINxN terminals decouples the driving op amp from the sampling
glitch. It is recommended to split the series resistance of the input filter in two equal values as shown in
Figure 86. It is recommended that both input terminals see the same impedance from the external circuit. The
low-pass filter at the input limits noise bandwidth of the driving op amps. Select the filter bandwidth so that the
full-scale step at the input can settle to the required accuracy during the sampling time. Equation 1, Equation 2,
and Equation 3 are useful for filter component selection.
Where:
Settling resolution is the accuracy in LSB to which the input needs to settle. A typical settling resolution
for the 14-bit device is 15 or 16. (1)
(2)
(3)
Also, make sure the driving op amp bandwidth does not limit the signal bandwidth below filter bandwidth. In
many applications, signal bandwidth may be much lower than filter bandwidth. In this case, an additional
low-pass filter may be used at the input of the driving op amp. This signal filter bandwidth can be selected in
accordance with the input signal bandwidth.
INPUT COMMON-MODE RANGE
The AIN+ and AIN– inputs to the ADS7945 should typically vary between 0 V and V
REF
with a common-mode of
V
REF
/2. The ADS7945 offers excellent CMRR which makes it possible to achieve close to the rated performance
of the converter even in cases where the common-mode input is not well-controlled. The device can accept a
±200 mV variation in the common-mode voltage at any VDD/V
REF
combination allowing use of the entire ADC
signal range (–V
REF
to +V
REF
differentially).
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