Datasheet

1 2
15 16
1 2
15 16
1 2 11 12
13
14
15 16
t
PDSU
t
PDH
Sample
N 1-
Sample
N
Dummy
Sample
DataFromSample
N 2-
DataFromSample
N 1-
DataFromSample
N
SCLK
CS
SDO
Power-Down
(Internal)
PDEN
1 2
15 16
1 2
15 16
1
2
t
PDSU
Sample
N+1
Sample
N+2
InvalidData
SCLK
CS
SDO
Power-Down
(Internal)
PDEN
Sample
N+3
DataFromSample
N+1
DataFromSample
N+2
t
W1
+1 sm
ADS7945
ADS7946
SBAS539B –JUNE 2011– REVISED SEPTEMBER 2011 www.ti.com
In some applications, data collection is accomplished in burst mode. The system powers down after data
collection. 16-clock mode is convenient for these applications. Figure 84 and Figure 85 detail power saving in
16-clock burst mode.
Figure 84. Entry Into Power-Down with 16-Clock Burst Mode
As shown in Figure 84, the two frames capturing the N–1 and Nth samples are normal 16-clock frames. Keeping
PDEN = 1 before the CS rising edge in the next frame ensures that the devices detect the power-down mode.
Data from the Nth sample are read during this frame. It is expected that the Nth sample represents the last data
of interest in the burst of conversions. The devices enter the power-down state after the end of conversions. This
is the 16th SCLK falling edge. It is recommended to stop the clock after the 16th SCLK falling edge. Note that it
is mandatory not to have more than 29 SCLK falling edges during the CS low period. This limitation ensures that
the devices remain in 16-clock mode.
The devices remain in a power-down state as long as CS is low. A CS rising edge with PDEN = 0 brings the
devices out of the power-down state. It is necessary to ensure that the CS high time for the first sample after
power up is more than 1 µs + t
ACQ
(min).
Figure 85. Exit From Power-Down with 16-Clock Burst Mode
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