Datasheet

SCL
SDA
t
R
t
HDSTA
t
HDSTA
t
HDDAT
t
BUF
t
HIGH
t
SUSTA
t
SUSTO
P S Sr P
t
SP
t
VDACK
t
SUDAT
9thClock
t
VDDAT
t
F
t
LOW
ADS7924
www.ti.com SBAS482A –JANUARY 2010–REVISED MAY 2010
TIMING DIAGRAM
NOTE: S = Start, Sr = Repeated Start, and P = Stop.
Figure 1. I
2
C Timing Diagram
Table 1. I
2
C Timing Definitions
ADS7924
PARAMETER MIN MAX UNIT
SCL operating frequency f
SCL
0 0.4 MHz
Bus free time between START and STOP condition t
BUF
1.3 ms
Hold time after repeated START condition.
t
HDSTA
600 ns
After this period, the first clock is generated.
Repeated START condition setup time t
SUSTA
600 ns
Stop condition setup time t
SUSTO
600 ns
Data hold time t
HDDAT
0 ns
Data setup time t
SUDAT
100 ns
SCL clock low period t
LOW
1300 ns
SCL clock high period t
HIGH
600 ns
Clock/data fall time t
F
300 ns
Clock/data rise time t
R
300 ns
Data valid time t
VDDAT
0.9 ms
Data valid acknowledge time t
VDACK
0.9 ms
Pulse width of spike that must be suppressed by the input filter t
SP
0 50 ns
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