Datasheet

ADS7924
www.ti.com SBAS482A –JANUARY 2010–REVISED MAY 2010
I
2
C INTERFACE Every byte transmitted on the I
2
C bus, whether it is
address or data, is acknowledged with an
The ADS7924 communicates through an I
2
C
acknowledge bit. When the master has finished
interface. I
2
C is a two-wire, open-drain interface that
sending a byte (eight data bits) to a slave, it stops
supports multiple devices and masters on a single
driving SDA and waits for the slave to acknowledge
bus. Devices on the I
2
C bus only drive the bus lines
the byte. The slave acknowledges the byte by pulling
low by connecting them to ground; they never drive
SDA low. The master then sends a clock pulse to
the bus lines high. Instead, the bus wires are pulled
clock the acknowledge bit. Similarly, when the master
high by pull-up resistors, so the bus wires are high
has finished reading a byte, it pulls SDA low to
when no device is driving them low. This way, two
acknowledge this to the slave. It then sends a clock
devices cannot conflict; if two devices drive the bus
pulse to clock the bit. (The master always drives the
simultaneously, there is no driver contention.
clock line.)
Communication on the I
2
C bus always takes place
A not-acknowledge is performed by simply leaving
between two devices, one acting as the master and
SDA high during an acknowledge cycle. If a device is
the other as the slave. Both masters and slaves can
not present on the bus, and the master attempts to
read and write, but slaves can only do so under the
address it, it receives a not-acknowledge because no
direction of the master. Some I
2
C devices can act as
device is present at that address to pull the line low.
masters or slaves, but the ADS7924 can only act as
a slave device. When the master has finished communicating with a
slave, it may issue a STOP condition. When a STOP
An I
2
C bus consists of two lines, SDA and SCL. SDA
condition is issued, the bus becomes idle again. The
carries data; SCL provides the clock. All data are
master may also issue another START condition.
transmitted across the I
2
C bus in groups of eight bits.
When a START condition is issued while the bus is
To send a bit on the I
2
C bus, the SDA line is driven to
active, it is called a repeated START condition.
the appropriate level while SCL is low (a low on SDA
indicates the bit is zero; a high indicates the bit is See the Timing Diagrams section for a timing
one). Once the SDA line settles, the SCL line is diagram showing the ADS7924 I
2
C transaction.
brought high, then low. This pulse on SCL clocks the
SDA bit into the receiver shift register. If the I
2
C bus
I
2
C ADDRESS SELECTION
is held idle for more than 25ms, the bus times out.
The ADS7924 has one address pin, A0, that sets the
The I
2
C bus is bidirectional: the SDA line is used for
I
2
C address. This pin can be connected to ground or
both transmitting and receiving data. When the
VDD, allowing two addresses to be selected with one
master reads from a slave, the slave drives the data
pin as shown in Table 5. The state of the address pin
line; when the master sends to a slave, the master
A0 is sampled continuously.
drives the data line. The master always drives the
clock line. The ADS7924 never drives SCL, because
Table 5. A0 Pin Connection and Corresponding
it cannot act as a master. On the ADS7924, SCL is Slave Address
an input only.
A0 PIN SLAVE ADDRESS
Most of the time the bus is idle; no communication
Ground 1001000
occurs, and both lines are high. When communication
DVDD 1001001
is taking place, the bus is active. Only master devices
can start a communication and initiate a START
I
2
C SPEED MODES
condition on the bus. Normally, the data line is only
allowed to change state while the clock line is low. If
The ADS7924 supports the I
2
C standard and fast
the data line changes state while the clock line is
modes. Standard mode allows a clock frequency of
high, it is either a START condition or a STOP
up to 100kHz and fast mode permits a clock
condition. A START condition occurs when the clock
frequency of up to 400kHz.
line is high and the data line goes from high to low. A
STOP condition occurs when the clock line is high
SLAVE MODE OPERATIONS
and the data line goes from low to high.
The ADS7924 can act as either slave receivers or
After the master issues a START condition, it sends a
slave transmitters. As a slave device, the ADS7924
byte that indicates which slave device it wants to
cannot drive the SCL line.
communicate with. This byte is called the address
byte. Each device on an I
2
C bus has a unique 7-bit
address to which it responds. The master sends an
address in the address byte, together with a bit that
indicates whether it wishes to read from or write to
the slave device.
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