Datasheet

ADS7924

SBAS482A –JANUARY 2010–REVISED MAY 2010

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INTCONFIG: Interrupt Configuration Register (Address = 12h)

7 6 5 4 3 2 1 0

ALMCNT2 ALMCNT1 ALMCNT0 INTCNFG2 INTCNFG1 INTCNFG0 INTPOL INTTRIG

Bits[7:5] ALMCNT[2:0]: Alarm count

These bits set the number of times the comparator threshold limit (either upper or lower) must be exceeded to generate an

alarm.

000 = Every conversion generates an alarm

010 = Exceeding the threshold limit 1 time generates an alarm condition

100 = Exceeding the threshold limit 2 times generates an alarm condition

110 = Exceeding the threshold limit 3 times generates an alarm condition

111 = Exceeding the threshold limit 4 times generates an alarm condition

101 = Exceeding the threshold limit 5 times generates an alarm condition

110 = Exceeding the threshold limit 6 times generates an alarm condition

111 = Exceeding the threshold limit 7 times generates an alarm condition

Bits[4:2] INTCNFG[2:0]: INT output pin configuration

These bits determine which signal is output on INT. They also select the conversion control event; see the CONVCTRL bit

in the SLPCONFIG register. The configuration of these bits is shown in Table 4.

Table 4. INT Pin Configuration

BIT SETTING INT PIN CONFIGURATION CONVERSION CONTROL EVENT

000 Alarm Alarm

001 Busy Alarm

010 Data ready: one conversion completed Data ready: one conversion complete

011 Busy Data ready: one conversion complete

100 Do not use —

101 Do not use —

110 Data ready: all four conversions complete Data ready: four conversions complete

111 Busy Data ready: four conversions complete

Bit 1 INTPOL: INT pin polarity

0 = Active low (default)

1 = Active high

Bit 0 INTTRIG: INT output pin signaling

0 = Static signal for use with level triggering (default)

1 = Pulse signal for use with edge triggering

Product Folder Link(s): ADS7924