Datasheet

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SBAS482A –JANUARY 2010–REVISED MAY 2010

There are individual upper and lower threshold registers for input channel. Each register is eight bits with the

least significant bit weight equal to AVDD/256. The comparator is tripped when the input signal exceeds the

value of the upper limit register or falls below the lower limit register.

ULR0: Upper Limit Threshold for Channel 0 Comparator Register (Address = 0Ah)

7 6 5 4 3 2 1 0

ULR0[7] (MSB) ULR0[6] ULR0[5] ULR0[4] ULR0[3] ULR0[2] ULR0[1] ULR0[0] (LSB)

LLR0: Lower Limit Threshold for Channel 0 Comparator Register (Address = 0Bh)

7 6 5 4 3 2 1 0

LLR0[7] (MSB) LLR0[6] LLR0[5] LLR0[4] LLR0[3] LLR0[2] LLR0[1] LLR0[0] (LSB)

ULR1: Upper Limit Threshold for Channel 1 Comparator Register (Address = 0Ch)

7 6 5 4 3 2 1 0

ULR1[7] (MSB) ULR1[6] ULR1[5] ULR1[4] ULR1[3] ULR1[2] ULR1[1] ULR1[0] (LSB)

LLR1: Lower Limit Threshold for Channel 1 Comparator Register (Address = 0Dh)

7 6 5 4 3 2 1 0

LLR1[7] (MSB) LLR1[6] LLR1[5] LLR1[4] LLR1[3] LLR1[2] LLR1[1] LLR0[0] (LSB)

ULR2: Upper Limit Threshold for Channel 2 Comparator Register (Address = 0Eh)

7 6 5 4 3 2 1 0

ULR2[7] (MSB) ULR2[6] ULR2[5] ULR2[4] ULR2[3] ULR2[2] ULR2[1] ULR2[0] (LSB)

LLR2: Lower Limit Threshold for Channel 2 Comparator Register (Address = 0Fh)

7 6 5 4 3 2 1 0

LLR2[7] (MSB) LLR2[6] LLR2[5] LLR2[4] LLR2[3] LLR2[2] LLR2[1] LLR2[0] (LSB)

ULR3: Upper Limit Threshold for Channel 3 Comparator Register (Address = 10h)

7 6 5 4 3 2 1 0

ULR3[7] (MSB) ULR3[6] ULR3[5] ULR3[4] ULR3[3] ULR3[2] ULR3[1] ULR3[0] (LSB)

LLR3: Lower Limit Threshold for Channel 3 Comparator Register (Address = 11h)

7 6 5 4 3 2 1 0

LLR3[7] (MSB) LLR3[6] LLR3[5] LLR3[4] LLR3[3] LLR3[2] LLR3[1] LLR3[0] (LSB)

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