Datasheet

ADS7924
SBAS482A –JANUARY 2010–REVISED MAY 2010 www.ti.com
There are individual registers for each input channel to buffer the conversion data. The 12 bits are stored in two
registers: the upper register stores the eight most significant bits; the lower register stores the lower four least
significant bits. The data registers are always updated with the corresponding input channel regardless of the
order of conversion. For example, DATA0_U and DATA0_L always contain the results of the latest conversion of
CH0.
DATA0_U: Conversion Data for Channel 0, Upper Bits Register (Address = 02h)
7 6 5 4 3 2 1 0
DATA0[11]
DATA0[10] DATA0[9] DATA0[8] DATA0[7] DATA0[6] DATA0[5] DATA0[4]
(MSB)
DATA0_L: Conversion Data for Channel 0, Lower Bits Register (Address = 03h)
7 6 5 4 3 2 1 0
DATA0[0]
DATA0[3] DATA0[2] DATA0[1] 0 0 0 0
(LSB)
DATA1_U: Conversion Data for Channel 1, Upper Bits Register (Address = 04h)
7 6 5 4 3 2 1 0
DATA1[11]
DATA1[10] DATA1[9] DATA1[8] DATA1[7] DATA1[6] DATA1[5] DATA1[4]
(MSB)
DATA1_L: Conversion Data for Channel 1, Lower Bits Register (Address = 05h)
7 6 5 4 3 2 1 0
DATA1[0]
DATA1[3] DATA1[2] DATA1[1] 0 0 0 0
(LSB)
DATA2_U: Conversion Data for Channel 2, Upper Bits Register (Address = 06h)
7 6 5 4 3 2 1 0
DATA2[11]
DATA2[10] DATA2[9] DATA2[8] DATA2[7] DATA2[6] DATA2[5] DATA2[4]
(MSB)
DATA2_L: Conversion Data for Channel 2, Lower Bits Register (Address = 07h)
7 6 5 4 3 2 1 0
DATA2[0]
DATA2[3] DATA2[2] DATA2[1] 0 0 0 0
(LSB)
DATA3_U: Conversion Data for Channel 3, Upper Bits Register (Address = 08h)
7 6 5 4 3 2 1 0
DATA3[11]
DATA3[10] DATA3[9] DATA3[8] DATA3[7] DATA3[6] DATA3[5] DATA3[4]
(MSB)
DATA3_L: Conversion Data for Channel 3, Lower Bits Register (Address = 09h)
7 6 5 4 3 2 1 0
DATA3[0]
DATA3[3] DATA3[2] DATA3[1] 0 0 0 0
(LSB)
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