Datasheet

AVDD
AGND
CH0
AVDD
AGND
CH1
AVDD
AGND
CH2
AVDD
AGND
CH3
MUXOUT
AGND
(1)
FFF
OutputCode(Hex)
0
¼
InputVoltage(V )
ACDIN
FFE
800
¼
000
7FE
001
¼
AVDD
AVDD 1.5LSB-0.5LSB
1LSB=AVDD/2
12
ADS7924
SBAS482A –JANUARY 2010–REVISED MAY 2010 www.ti.com
MULTIPLEXER capacitor is connected to the ADCIN pin. While
converting during the t
CONV
interval, the sampling
The ADS7924 has a four-channel, single-ended input
capacitor is disconnected from the ADCIN pin, and
multiplexer. As Figure 20 shows, ESD diodes protect
the conversion process determines the voltage that
the inputs. Make sure these diodes do not turn on by
was sampled.
staying within the absolute input voltage range
specification. The MUXOUT pin can be connected to
REFERENCE
AGND within the multiplexer; for example, to provide
a test signal of 0V or as part of a calibration
The analog supply voltage (AVDD) is used as the
procedure. See the PWRCONFIG: Power
reference. Power to the ADS7924 should be clean
Configuration register in the Register Map section for
and well bypassed. A 0.1mF ceramic capacitor should
more details
be placed as close as possible to the ADS7924
package. In addition, a 1mF to 10mF capacitor and a
5Ω to 10Ω series resistor may be used to low-pass
filter a noisy supply.
CLOCK
The ADS7924 uses an internal clock. The clock
speed determines the various timing settings such as
conversion time, acquisition time, etc.
DATA FORMAT
The ADS7924 provides 12 bits of data in unipolar
format. The positive full-scale input produces an
output code of FFFh and a zero input produces an
output code of 0h. The output clips at these codes for
signals that either exceed full-scale or go below '0'.
Figure 21 shows code transitions versus input
voltage.
(1) See the PWRCONFIG: Power Configuration register in the
Register Map section.
Figure 20. ADS7924 Multiplexer
ADC INPUT
The ADCIN pin provides a single-ended input to the
12-bit successive approximation register (SAR) ADC.
This pin is protected with ESD diodes in the same
way as the multiplexer inputs. While acquiring the
signal during the t
ACQ
interval, the ADC sampling
(1) Excludes the effects of noise, INL, offset, and gain errors.
Figure 21. ADS7924 Code Transition Diagram
(1)
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