Datasheet

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ADS7887 SPECIFICATIONS
ADS7887
ADS7888
SLAS468 JUNE 2005
+V
DD
= 2.35 V to 5.25 V, T
A
= –40 ° C to 125 ° C, f
sample
= 1.25 MHz
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ANALOG INPUT
Full-scale input voltage span
(1)
0 V
DD
V
Absolute input voltage range +IN –0.20 V
DD
+0.20 V
C
i
Input capacitance
(2)
21 pF
I
Ilkg
Input leakage current T
A
= 125 ° C 40 nA
SYSTEM PERFORMANCE
Resolution 10 Bits
No missing codes 10 Bits
INL Integral nonlinearity –0.75 ± 0.35 0.75 LSB
(3)
DNL Differential nonlinearity –0.5 ± 0.35 0.5 LSB
E
O
Offset error
(4) (5) (6)
–1.5 ± 0.5 1.5 LSB
E
G
Gain error
(5)
–1 ± 0.5 1 LSB
SAMPLING DYNAMICS
Conversion time 25-MHz SCLK 530 560 ns
Acquisition time 260 ns
Maximum throughput rate 25-MHz SCLK 1.25 MHz
Aperture delay 5 ns
Step Response 160 ns
Overvoltage recovery 160 ns
DYNAMIC CHARACTERISTICS
THD Total harmonic distortion
(7)
100 kHz –84 –72 dB
SINAD Signal-to-noise and distortion 100 kHz 60.5 61 dB
SFDR Spurious free dynamic range 100 kHz 73 81 dB
Full power bandwidth At –3 dB 15 MHz
DIGITAL INPUT/OUTPUT
Logic family CMOS
VDD = 2.35 V to 5.25 V V
DD
5.25
V
IH
High-level input voltage V
0.4
V
DD
= 5 V 0.8
V
IL
Low-level input voltage V
V
DD
= 3 V 0.4
V
OH
High-level output voltage At I
source
= 200 µA V
DD
–0.2
V
V
OL
Low-level output voltage At I
sink
= 200 µA 0.4
POWER SUPPLY REQUIREMENTS
+V
DD
Supply voltage 2.35 3.3 5.25 V
At V
DD
= 2.35 V to 5.25 V, 1.25-MHz throughput 2
Supply current (normal mode) mA
At V
DD
= 2.35 V to 5.25 V, static state 1.5
SCLK off 1
Power down state supply current µA
SCLK on (25 MHz) 200
V
DD
= 5 V 8 10
Power dissipation at 1.25 MHz
mW
throughput
V
DD
= 3 V 3.8 6
(1) Ideal input span; does not include gain or offset error.
(2) Refer Figure 36 for details on sampling circuit
(3) LSB means least significant bit
(4) Measured relative to an ideal full-scale input
(5) Offset error and gain error ensured by characterization.
(6) First transition of 000H to 001H at 0.5 × (V
ref
/2
10
)
(7) Calculated on the first nine harmonics of the input frequency
4