Datasheet

1 2 3 4 5 9
10 16
CS
SCLK
SDO
t
d5
t
d6
Invalid Data Valid Data
SDO
1 5432 6 10987 131211 161514 1 5432 6 10987 131211 161514
SCLK
Device Fully
Powered-Up
Device Starts
Powering Up
CS
ADS7886
www.ti.com SLAS492A –SEPTEMBER 2005–REVISED NOVEMBER 2009
POWER DOWN MODE
The device enters power down mode if CS goes high anytime after the 2nd SCLK falling edge to before the 10th
SCLK falling edge. Ongoing conversion stops and SDO goes to 3-state under this power down condition as
shown in Figure 2.
Figure 2. Entering Power Down Mode
A dummy cycle with CS low for more than 10 SCLK falling edges brings the device out of power down mode. For
the device to come to the fully powered up condition it takes 1 µs. CS can be pulled high any time after the 10th
falling edge as shown in Figure 3. It is not necessary to continue until the 16th clock if the next conversion starts
1 µs after CS going low of the dummy cycle and the quiet time (t
q
) condition is met.
Figure 3. Exiting Power Down Mode
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