Datasheet

ADS7886
www.ti.com SLAS492A –SEPTEMBER 2005–REVISED NOVEMBER 2009
TIMING REQUIREMENTS (see Figure 1 and Figure 2)
All specifications typical at T
A
= –40°C to 125°C, V
DD
= 2.35 V to 5.25 V (unless otherwise specified).
PARAMETER TEST CONDITIONS
(1)
MIN TYP MAX UNIT
V
DD
= 3 V 16 × t
SCLK
t
conv
Conversion time ADS7866 ns
V
DD
= 5 V 16 × t
SCLK
V
DD
= 3 V 40
Minimum quiet time needed from bus 3-state to start
t
q
ns
of next conversion
V
DD
= 5 V 40
V
DD
= 3 V 15 25
t
d1
Delay time, CS low to first data (0) out ns
V
DD
= 5 V 13 25
V
DD
= 3 V 10
t
su1
Setup time, CS low to SCLK low ns
V
DD
= 5 V 10
V
DD
= 3 V 15 25
t
d2
Delay time, SCLK falling to SDO ns
V
DD
= 5 V 13 25
V
DD
< 3 V 7
t
h1
Hold time, SCLK falling to data valid
(2)
ns
V
DD
> 5 V 5.5
V
DD
= 3 V 10 25
t
d3
Delay time, 16th SCLK falling edge to SDO 3-state ns
V
DD
= 5 V 8 20
V
DD
= 3 V 25 40
t
w1
Pulse duration, CS ns
V
DD
= 5 V 25 40
V
DD
= 3 V 17 30
t
d4
Delay time, CS high to SDO 3-state ns
V
DD
= 5 V 15 25
V
DD
= 3 V 0.4 × t
SCLK
t
wH
Pulse duration, SCLK high ns
V
DD
= 5 V 0.4 × t
SCLK
V
DD
= 3 V 0.4 × t
SCLK
t
wL
Pulse duration, SCLK low ns
V
DD
= 5 V 0.4 × t
SCLK
V
DD
= 3 V 20
Frequency, SCLK MHz
V
DD
= 5 V 20
Delay time, second falling edge of clock and CS to V
DD
= 3 V -2 5
t
d5
enter in powerdown (use min spec not to accidently ns
V
DD
= 5 V -2 5
enter in powerdown) Figure 2
Delay time, CS and 10th falling edge of clock to V
DD
= 3 V 2 -5
t
d6
enter in powerdown (use max spec not to accidently ns
V
DD
= 5 V 2 -5
enter in powerdown) Figure 2
(1) 3-V Specifications apply from 2.35 V to 3.6 V, and 5-V specifications apply from 4.75 V to 5.25 V.
(2) With 50-pf load.
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