Datasheet

4 Digital Interface
www.ti.com Digital Interface
The ADS788xEVM is designed for easy interfacing to multiple platforms. Samtec part numbers
SSW-110-22-F-D-VS-K and TSM-110-01-T-DV-P provide a convenient dual row header/socket
combination at P1 and P2. Consult Samtec at www.samtec.com or 1-800-SAMTEC-9 for a variety of
mating connector options.
The digital input and output signals for the converter is made available via connector P2 on the
ADS7886EVM/ADS7887EVM/ADS7888EVM, see Table 4 for connector pin-out.
Table 4. Serial Control Connector P2
Connector and Pin
Description Signal Name Number Signal Name Description
Chip Select CS P2.1 P2.2 N/C Reserved
Serial Clock SCLK P2.3 P2.4 DGND Ground
Reserved N/C P2.5 P2.6 N/C Reserved
Frame Sync FS P2.7 P2.8 N/C Reserved
Reserved N/A P2.9 P2.10 DGND Ground
Reserved N/C P2.11 P2.12 N/C Reserved
Serial Data Out SDO P2.13 P2.14 N/C Reserved
Reserved N/C P2.15 P2.16 N/C Reserved
Reserved N/C P2.17 P2.18 DGND Ground
Reserved N/C P2.19 P2.20 N/A Reserved
I/O buffer and level translation functions may not be required for many applications. These devices have a
high-level digital input that is not limited to the device VDD voltage, but to 5.25 V. This different limit
means that the ADC can be powered up at 2.35 V and interfaced to 5-V logic directly.
The ADS788x output low-level and high-level voltages are 0.4 V and (VDD – 0.2 V), respectively. If the
ADS788x is powered up at 5 V and the host processor is at 1.8 V, then level translation may be required.
The output level translation function (done by U6 on the EVM) may be required depending on the host
processor. Check the specific host processor data sheet for input logic levels.
SLAU166B – October 2005 – Revised August 2008 ADS788xEVM 9
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