Datasheet

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SLAS400B − SEPTEMBER 2003 − REVISED NOVEMBER 2005
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5
TIMING REQUIREMENTS
All specifications typical at −40°C to 85°C, +VA = +5 V, +VBD = +5 V (see Notes 1, 2, 3, and 4)
PARAMETER SYMBOL MIN TYP MAX UNITS REF FIG.
Conversion time t
(conv)
185 200 ns 5
Acquisition time t
(acq)
50 65 ns 5
SAMPLING AND CONVERSION START
Hold time CS low to CONVST high (with BUSY high) t
h1
10 ns 3
Delay CONVST high to acquisition start t
d1
2 4 5 ns 1
Hold time, CONVST high to CS high with BUSY low t
h2
10 ns 1
Hold time, CONVST low to CS high t
h3
10 ns 1
Delay CONVST low to BUSY high t
d2
40 ns 1
CS width for acquisition or conversion to start t
w3
20 ns 2
Delay CS low to acquisition start with CONVST high t
d3
2 4 5 ns 2
Pulse width, from CS low to CONVST low for acquisition to start t
w1
20 ns 2
Delay CS low to BUSY high with CONVST low t
d4
40 ns 2
Quiet sampling time
(3)
25 ns
CONVERSION ABORT
Setup time CONVST high to CS low with BUSY high t
s1
15 ns 4
Delay time CS low to BUSY low with CONVST high t
d5
20 ns 4
DATA READ
Delay RD low to data valid with CS low t
d6
25 ns 5
Delay BYTE high to LSB word valid with CS and RD low t
d7
25 ns 5
Delay time RD high to data 3-state with CS low t
d9
25 ns 5
Delay time end of conversion to BUSY low t
d11
20 ns 5
Quiet sampling time RD high to CONVST low t
1
25 ns 5
Delay CS low to data valid with RD low t
d8
25 ns 6
Delay CS high to data 3-state with RD low t
d10
25 ns 6
Quiet sampling time CS low to CONVST low t
2
25 ns 6
BACK-TO-BACK CONVERSION
Delay BUSY low to data valid t
d12
10 ns 7, 8
Pulse width, CONVST high t
w4
60 ns 7, 8
Pulse width, CONVST low t
w5
20 ns 7
POWER DOWN/RESET
Pulse width, low for PWD/RST to reset the device t
w6
45 6140 ns 10
Pulse width, low for PWD/RST to power down the device t
w7
7200 ns 9
Delay time, power up after PWD/RST is high t
d13
25 ms 9
(1)
All input signals are specified with t
r
= t
f
= 5 ns (10% to 90% of +VBD) and timed from a voltage level of (V
IL
+ V
IH
)/2.
(2)
See timing diagram.
(3)
Quiet period before conversion start, no data bus activity including data bus 3-state is allowed in this period.
(4)
All timings are measured with 20 pF equivalent loads on all data bits and BUSY pin.