Datasheet


SLAS400B − SEPTEMBER 2003 − REVISED NOVEMBER 2005
www.ti.com
22
APPLICATION INFORMATION
LAYOUT
For optimum performance, care should be taken with the physical layout of the ADS7881 circuitry.
As the ADS7881 offers single-supply operation, it is often used in close proximity with digital logic,
micro-controllers, microprocessors, and digital signal processors. The more digital logic present in the design
and the higher the switching speed, the more difficult it is to achieve acceptable performance from the converter.
The basic SAR architecture is sensitive to glitches or sudden changes on the power supply, reference, ground
connections, and digital inputs that occur just prior to the end of sampling (within quiet sampling time) and just
prior to latching the output of the analog comparator during the conversion phase. Thus, driving any single
conversion for an n-bit SAR converter, there are n+1 windows in which large external transient voltages can
affect the conversion result. Such glitches might originate from switching power supplies, nearby digital logic,
or high power devices.
The degree of error in the digital output depends on the reference voltage, layout, and the exact timing of the
external event.
On average, the ADS7881 draws very little current from an external reference as the reference voltage is
internally buffered. If the reference voltage is external and originates from an op amp, make sure that it can drive
the bypass capacitor or capacitors without oscillation. A 0.1-µF bypass capacitor and 1-µF storage capacitor
are recommended from REFIN (pin 1) directly to REFM (pin 48).
The AGND and BDGND pins should be connected to a clean ground point. In all cases, this should be the analog
ground. Avoid connections which are too close to the grounding point of a micro-controller or digital signal
processor. If required, run a ground trace directly from the converter to the power supply entry point. The ideal
layout consists of an analog ground plane dedicated to the converter and associated analog circuitry.
As with the AGND connections, +VA should be connected to a 5-V power supply plane that is separate from
the connection for +VBD and digital logic until they are connected at the power entry point onto the PCB. Power
to the ADS7881 should be clean and well bypassed. A 0.1-µF ceramic bypass capacitor should be placed as
close to the device as possible. See Table 3 for the placement of capacitor. In addition to a 0.1-µF capacitor,
a 1-µF capacitor is recommended. In some situations, additional bypassing may be required, such as a 100-µF
electrolytic capacitor or even a Pi filter made up of inductors and capacitors, all designed to essentially low-pass
filter the 5-V supply, removing the high frequency noise.
Table 3. Power Supply Decoupling Capacitor Placement
POWER SUPPLY PLANE
CONVERTER ANALOG SIDE
CONVERTER DIGITAL SIDE
SUPPLY PINS
CONVERTER ANALOG SIDE
CONVERTER DIGITAL SIDE
Pairs of pins that require a shortest path to decoupling
capacitors
(4,5), (9,8), (10,11), (13, 15), (43, 44) (46, 45) (24, 25), (34, 35)
Pins that require no decoupling 14, 12
21 Ω
0.1 µF
1 µF
0.1 µF
0.1 µF
1 µF
Analog Input
Circuit
21 Ω
+VA
AGND
REFOUT
REFIN
REFM
+IN
−IN
ADS7881
Analog 5 V
AGND
External
Reference in
AGND
Figure 37. Using External Reference