Datasheet

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SLAS400B − SEPTEMBER 2003 − REVISED NOVEMBER 2005
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21
Table 1. Ideal Input Voltages and Output Codes
(1)
DESCRIPTION ANALOG VALUE BINARY CODE HEX CODE
Full scale V
ref
− 1 LSB 1111 1111 1111 FFF
Midscale V
ref
/2 1000 0000 0000 800
Midscale − 1 LSB V
ref
/2 − 1 LSB 0111 1111 1111 7FF
Zero 0 V 0000 0000 0000 000
(1)
Full-scale range = V
ref
and least significant bit (LSB) = V
ref
/4096
The output data appears as a full 12-bit word (D11−D0) on pins DB11 – DB0 (MSB−LSB) if BYTE is low.
READING THE DATA IN BYTE MODE
The result can also be read on an 8-bit bus for convenience by using pins DB11−DB4. In this case two reads
are necessary; the first as before, leaving BYTE low and reading the 8 most significant bits on pins DB11−DB4,
and then bringing BYTE high. When BYTE is high, the lower bits (D3−D0) followed by all zeros are on pins DB11
− DB4 (refer to Table 2).
These multi-word read operations can be performed with multiple active RD signals (toggling) or with RD tied
low for simplicity.
Table 2. Conversion Data Read Out
BYTE
DATA READ OUT
BYTE
DB11 − DB4 DB3 − DB0
High D3 − D0, 0000 All zeroes
Low D11 − D4 D3 − D0
Also refer to the DATA READ and DEVICE OPERATION AND DATA READ IN BACK-TO-BACK
CONVERSION sections for more details.
Reset
Refer to the POWERDOWN/RESET section for the device reset sequence.
It is recommended to reset the device after power on. A reset can be issued once the power has reached 95%
of its final value.
PWD/RST is an asynchronous active low input signal. A current conversion is aborted no later than 45 ns after
the converter is in the reset mode. In addition, the device outputs a FE0 code to indicate a reset condition. The
converter returns back to normal operation mode immediately after the PWD/RST input is brought high.
Data is not valid for the first four conversions after a device reset.
Powerdown
Refer to the POWERDOWN/RESET section for the device powerdown sequence.
The device enters powerdown mode if a PWD/RST low duration is extended for more than a period of t
w7
.
The converter goes back to normal operation mode no later than a period of t
d13
after the PWD/RST input is
brought high.
After this period, normal conversion and sampling operation can be started as discussed in previous sections.
Data is not valid for the first four conversions after a device reset.
Nap Mode
Refer to the NAP MODE section in the DESCRIPTION AND TIMING DIAGRAMS section for information.