Datasheet

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SLAS400B − SEPTEMBER 2003 − REVISED NOVEMBER 2005
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12
t
(acq)
+ 60 ns
A_PWD
BUSY
SAMPLE
(Internal)
NAP
(Internal Active High)
NOTE
:
The SAMPLE (Internal) signal is generated as described in the Sampling and Conversion
Start section.
Figure 10. Device Operation While A_PWD is Toggling
POWERDOWN/RESET
A low level on the PWD/RST pin puts the device in the powerdown phase. This is an asynchronous signal. As
shown in Figure 11, the device is in the reset phase for the first t
w6
period after a high-to-low transition of
PWD/RST. During this period the output code is FE0 (hex) to indicate that the device is in the reset phase. The
device powers down if the PWD/RST pin continues to be low for a period of more than t
w7
. Data is not valid for
the first four conversions after a power-up (see Figure 11) or an end of reset (see Figure 12). The device is
initialized during the first four conversions.
Power Down
Phase
1111 1110 0000
12345
PWD/RST
BUSY
D11−D0
t
d13
t
w7
First 4 Invalid Conversions
Valid Conversions
RESET Phase
Invalid Data Valid Data
Figure 11. Device Power Down
1111 1110 0000
12345
PWD/RST
BUSY
D11−D0
t
w6
First 4 Invalid Conversions
Valid Conversions
RESET Phase
Invalid Data Valid Data
45 ns
Figure 12. Device Reset