Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsData collecting ICsData acquisition IC - AD converter (ADC) External , Internal TQFP 48



SLAS400B − SEPTEMBER 2003 − REVISED NOVEMBER 2005

 

    

FEATURES

D 4 MHz Sample Rate, 12-Bit Resolution

D Zero Latency

D Unipolar, Pseudo Differential Input, Range:

− 0 V to 2.5 V

D High Speed Parallel Interface

D 71 dB SNR and −88.5 dB THD at 1 MHz I/P

D Power Dissipation 95 mW at 4 MSPS

D Nap Mode (10 mW Power Dissipation)

D Power Down (10 mW)

D Internal Reference

D Internal Reference Buffer

D 48-Pin TQFP and QFN Packages

APPLICATIONS

D Optical Networking (DWDM, MEMS Based

Switching)

D Spectrum Analyzers

D High Speed Data Acquisition Systems

D High Speed Close-Loop Systems

D Telecommunication

D Ultra-Sound Detection

DESCRIPTION

The ADS7881 is a 12-bit 4-MSPS A-to-D converter with

2.5-V internal reference. The device includes a capacitor

based SAR A/D converter with inherent sample and hold.

The device offers a 12-bit parallel interface with an

additional byte mode that provides easy interface with 8-bit

processors. The device has a pseudo-differential input

stage.

The −IN swing of ±200 mV is useful to compensate for

ground voltage mismatch between the ADC and sensor

and also to cancel common-mode noise. With nap mode

enabled, the device operates at lower power when used at

lower conversion rates. The device is available in 48-pin

TQFP and QFN packages.

SAR

Output

Latches

and

3-State

Drivers

BYTE

12/8-Bit Parallel

Data Output Bus

Conversion

and

Control Logic

CONVST

BUSY

A_PWDPWD/RST

CDAC

Comparator

CLOCK

2.5 V

Internal

Reference

+IN

−IN

REFIN

REFOUT

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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments

semiconductor products and disclaimers thereto appears at the end of this data sheet.

Summary of content (31 pages)

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SLAS400B − SEPTEMBER 2003 − REVISED NOVEMBER 2005 FEATURES D 4 MHz Sample Rate, 12-Bit Resolution D Zero Latency D Unipolar, Pseudo Differential Input, Range: D D D D D D D D − 0 V to 2.5 V High Speed Parallel Interface 71 dB SNR and −88.
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www.ti.com SLAS400B − SEPTEMBER 2003 − REVISED NOVEMBER 2005 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure.
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www.ti.com SLAS400B − SEPTEMBER 2003 − REVISED NOVEMBER 2005 SPECIFICATIONS TA = −40°C to 85°C, +VA = 5 V, +VBD = 5 V or 3.3 V, Vref = 2.5 V, fsample = 4 MHz (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ANALOG INPUT Full-scale input span(1) Absolute input range +IN – (−IN) 0 +IN −0.2 −IN −0.2 Input capacitance Input leakage current Vref Vref + 0.2 +0.
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www.ti.com SLAS400B − SEPTEMBER 2003 − REVISED NOVEMBER 2005 SPECIFICATIONS Continued TA = −40°C to 85°C, +VA = 5 V, +VBD = 5 V or 3.3 V, Vref = 2.5 V, fsample = 4 MHz (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT INTERNAL REFERENCE OUTPUT From 95% (+VA), with 1-µF storage capacitor on REFOUT to AGND Start-up time VREF Range Source current IOUT=0 Line regulation +VA = 4.75 V to 5.25 V Drift IOUT = 0 2.47 2.5 Static load 120 msec 2.
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www.ti.com SLAS400B − SEPTEMBER 2003 − REVISED NOVEMBER 2005 TIMING REQUIREMENTS All specifications typical at −40°C to 85°C, +VA = +5 V, +VBD = +5 V (see Notes 1, 2, 3, and 4) PARAMETER Conversion time Acquisition time SYMBOL t(conv) t(acq) MIN 50 TYP MAX UNITS REF FIG.
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www.ti.com SLAS400B − SEPTEMBER 2003 − REVISED NOVEMBER 2005 TERMINAL FUNCTIONS NAME NO. PFB NO.
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www.ti.com SLAS400B − SEPTEMBER 2003 − REVISED NOVEMBER 2005 DESCRIPTION AND TIMING DIAGRAMS SAMPLING AND CONVERSION START There are three ways to start sampling. The rising edge of CONVST starts sampling with CS and BUSY being low (see Figure 1) or it can be started with the falling edge of CS when CONVST is high and BUSY is low (see Figure 2).
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www.ti.com SLAS400B − SEPTEMBER 2003 − REVISED NOVEMBER 2005 CONVERSION ABORT The falling edge of CS aborts the conversion while BUSY is high and CONVST is high (see Figure 4). The device outputs FE0 (hex) to indicate a conversion abort. td5 BUSY tsu1 CONVST CS RD 1111 1110 0000 D11−D0 Figure 4. Conversion Abort DATA READ Two conditions need to be satisfied for a read operation. Data appears on the D11 through D0 pins (with D11 MSB) when both CS and RD are low.
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www.ti.com SLAS400B − SEPTEMBER 2003 − REVISED NOVEMBER 2005 t2 CONVST td1 + t(acq) BUSY Conversion No N td2 CS BYTE td7 D11−4 & D3−0 D11−D0 Data For Conv. N−1 td10 D3−0 Data For Conv. N td8 Figure 6. Read Control Via CS and RD Tied to BDGND DEVICE OPERATION AND DATA READ IN BACK-TO-BACK CONVERSION The following two figures illustrate device operation in back-to-back conversion mode.
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www.ti.com SLAS400B − SEPTEMBER 2003 − REVISED NOVEMBER 2005 CS Sample N th1 CONVST tw4 t(acq) tw3 t(conv) + td11 Conversion N BUSY Data For Conversion N−1 td12 D11−D0 (Data read Without Latency) t0 = 250 ns for 4 MSPS Operation Figure 8. Back-To-Back operation With CS Toggling and RD Low NAP MODE The device can be put in nap mode following the sequences shown in Figure 9. This provides substantial power saving while operating at lower sampling rates.
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www.ti.com SLAS400B − SEPTEMBER 2003 − REVISED NOVEMBER 2005 A_PWD BUSY SAMPLE (Internal) t(acq) + 60 ns NAP (Internal Active High) NOTE: The SAMPLE (Internal) signal is generated as described in the Sampling and Conversion Start section. Figure 10. Device Operation While A_PWD is Toggling POWERDOWN/RESET A low level on the PWD/RST pin puts the device in the powerdown phase. This is an asynchronous signal.
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www.ti.com SLAS400B − SEPTEMBER 2003 − REVISED NOVEMBER 2005 TYPICAL CHARACTERISTICS(1) EFFECTIVE NUMBER OF BITS vs FREE-AIR TEMPERATURE HISTOGRAM (DC CODE SPREAD AT THE CENTER OF CODE) 140000 Count 100000 80000 60000 40000 20000 Count =0 Count =1 2046 2047 0 2048 Count = 192 Count =0 2049 2050 ENOB − Effective Number of Bits − Bits 120000 12 Count = 130879 +VA = 5 V, +VBD = 5 V, Code = 2048, TA = 255C 11.9 11.8 11.7 11.6 11.5 11.4 11.3 11.2 11.
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www.ti.com SLAS400B − SEPTEMBER 2003 − REVISED NOVEMBER 2005 GAIN ERROR vs FREE-AIR TEMPERATURE OFFSET ERROR vs SUPPLY VOLTAGE 1.5 0.5 +VA = 5 V, +VBD = 5 V, +VBD = 5 V, TA = 25°C, 1.25 E G − Gain Error − mV EO − Offset Error − mV 0.4 0.3 0.2 0.1 1 0.75 0.5 0.25 0 4.75 4.8 4.85 4.9 4.95 5 5.05 5.1 5.15 5.2 5.
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www.ti.com SLAS400B − SEPTEMBER 2003 − REVISED NOVEMBER 2005 POWER DISSIPATION vs FREE-AIR TEMPERATURE DIFFERENTIAL NONLINEARITY vs FREE-AIR TEMPERATURE 97 1 DNL − Differential Nonlinearity − Bits PD − Power Dissipation − mW +VA = 5 V, +VBD = 5 V 96 95 94 93 −20 0 20 40 60 TA − Free-Air Temperature − °C 80 0.25 0 −0.25 Min −0.5 −0.75 −20 0 60 80 INTERNAL REFERENCE OUTPUT vs FREE-AIR TEMPERATURE 1 2.505 +VA = 5 V, +VBD = 5 V 2.
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www.ti.com SLAS400B − SEPTEMBER 2003 − REVISED NOVEMBER 2005 INTERNAL REFERENCE OUTPUT vs SUPPLY VOLTAGE 2.505 Vref − Internal Reference Output − V 2.5045 +VBD = 5 V, TA = 255C 2.504 2.5035 2.503 2.5025 2.502 2.5015 2.501 2.5005 2.5 4.75 4.8 4.85 4.9 4.95 5 5.05 5.1 5.15 5.2 5.25 +VA − Supply Voltage − V Figure 33 DNL − LSB DIFFERENTIAL NONLINEARITY 1 0.8 0.6 0.4 0.2 +VA = 5 V, +VBD = 5 V, TA = 25°C, Sample Rate = 4 MSPS 0 −0.2 −0.4 −0.6 −0.
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www.ti.com SLAS400B − SEPTEMBER 2003 − REVISED NOVEMBER 2005 FFT Signal Amplitude − dB 20 +VA = 5 V, +VBD = 5 V, TA = 25°C, Sample Rate = 4 MSPS 0 −20 −40 −60 −80 −100 −120 FIGURE 37 −140 −160 0 0.4 0.8 1.2 f − Frequency − MHz 1.
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www.ti.com SLAS400B − SEPTEMBER 2003 − REVISED NOVEMBER 2005 PRINCIPLES OF OPERATION The ADS7881 is a member of a family of high-speed successive approximation register (SAR) analog-to-digital converters (ADC). The architecture is based on charge redistribution, which inherently includes a sample/hold function. The conversion clock is generated internally. The conversion time is 200 ns max (at 5 V +VBD). The analog input is provided to two input pins: +IN and −IN.
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www.ti.com SLAS400B − SEPTEMBER 2003 − REVISED NOVEMBER 2005 Table 1. Ideal Input Voltages and Output Codes(1) DESCRIPTION Full scale ANALOG VALUE Vref − 1 LSB Vref/2 Midscale BINARY CODE HEX CODE 1111 1111 1111 FFF 1000 0000 0000 800 Midscale − 1 LSB Vref/2 − 1 LSB 0111 1111 1111 7FF Zero 0V 0000 0000 0000 000 (1) Full-scale range = Vref and least significant bit (LSB) = Vref/4096 The output data appears as a full 12-bit word (D11−D0) on pins DB11 – DB0 (MSB−LSB) if BYTE is low.
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www.ti.com SLAS400B − SEPTEMBER 2003 − REVISED NOVEMBER 2005 APPLICATION INFORMATION LAYOUT For optimum performance, care should be taken with the physical layout of the ADS7881 circuitry. As the ADS7881 offers single-supply operation, it is often used in close proximity with digital logic, micro-controllers, microprocessors, and digital signal processors.
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www.ti.com SLAS400B − SEPTEMBER 2003 − REVISED NOVEMBER 2005 Analog 5 V +VA 0.1 µF 1 µF ADS7881 AGND AGND REFOUT 0.1 µF 1 µF REFIN REFM AGND 21 Ω Analog Input Circuit 21 Ω +IN −IN Figure 38. Using Internal Reference 130 pF 604 Ω Signal Input 2.5 V DC 3 kΩ 604 Ω _ 100 Ω THS4211 + 1 kΩ 12 Ω 21 Ω 21 Ω 150 pF 1 nF +IN ADS7881 −IN AGND AGND Figure 39.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device ADS7881IPFBR Package Package Pins Type Drawing TQFP PFB 48 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 1000 330.0 16.4 9.6 9.6 1.5 12.0 16.0 Q2 ADS7881IPFBT TQFP PFB 48 250 330.0 16.4 9.6 9.6 1.5 12.0 16.0 Q2 ADS7881IRGZR VQFN RGZ 48 2500 330.0 16.4 7.3 7.3 1.5 12.0 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADS7881IPFBR TQFP PFB 48 1000 367.0 367.0 38.0 ADS7881IPFBT TQFP PFB 48 250 367.0 367.0 38.0 ADS7881IRGZR VQFN RGZ 48 2500 336.6 336.6 28.6 ADS7881IRGZT VQFN RGZ 48 250 336.6 336.6 28.
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MECHANICAL DATA MTQF019A – JANUARY 1995 – REVISED JANUARY 1998 PFB (S-PQFP-G48) PLASTIC QUAD FLATPACK 0,27 0,17 0,50 36 0,08 M 25 37 24 48 13 0,13 NOM 1 12 5,50 TYP 7,20 SQ 6,80 9,20 SQ 8,80 Gage Plane 0,25 0,05 MIN 0°– 7° 1,05 0,95 Seating Plane 0,75 0,45 0,08 1,20 MAX 4073176 / B 10/96 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C.
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