Datasheet

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6 Power Supplies
Power Supplies
This evaluation module provides direct access all the analog-to-digital converter control signals via
connector J3, see Table 6 .
Table 6. Pinout for Converter Control Connector J3
Connector.Pin
(1)
Signal Description
J3.1 CS Chip select pin. Active low.
J3.3 RD Read pin. Active low.
J3.5 CONVST Convert start pin. Active low.
J3.7 BYTE BYTE mode pin. Used for 8-bit buses.
J3.9 PWD/RST Active low input, acts as device power down/device reset signal.
J3.11 A_PDWN Nap mode enable, active low
J3.13 BUSY Converter status output. High when a conversion is in progress.
(1)
All even numbered pins of J3 are tied to DGND.
The EVM accepts four power supplies.
• A dual ± Vs DC supply for the dual supply op-amps. Recommend ± 12VDC supply.
• A single +5.0 V DC supply for analog section of the board (A/D + Reference).
• A single +5.0V or +3.3V DC supply for digital section of the board (A/D + address decoder + buffers).
There are two ways to provide these voltages.
• Wire in voltages at test points on the EVM. See Table below.
Table 7. Power Supply Test Points
Test Point Signal Description
TP11 +BVDD Apply +3.3VDC or +5.0VDC. See respective ADC datasheet for full range.
TP10 +AVCC Apply +5.0VDC.
TP12 +VA Apply +12.0VDC. Positive supply for amplifier.
TP14 –VA Apply -12.0VDC. Negative supply for amplifier.
• Use the power connector J1, and derive the voltages else where. The pin out for this connector is
below. Set jumper W5 to short between pins 1-2 or pins 2-3 to short +3.3VD or +5VD, respectively, to
be the buffer digital supply (+BVDD).
Table 8. Power Connector, J1, Pin Out
Signal Power Connector - J1 Signal
+VA (+12VA) 1 2 –VA (–12VA)
+AVCC(+5VA) 3 4 N/C
N/C 5 6 AGND
N/C 7 8 N/C
+3.3VD 9 10 +5VD
ADS7881/ADS7891EVM 6 SLAU150 – December 2004