Datasheet

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Digital Interface
Table 3. Pinout for Parallel Control Connector P2 (continued)
Connector.Pin
(1)
Signal Description
P2.19 BUSY Busy signal from converter. W4 must be shorted.
Read( RD), conversion start( CONVST) and reset ( RESET) signals to the converter can be assigned to two
different addresses in memory via jumper settings. This allows for the stacking of up to two
ADS7881EVM, and/or ADS7891EVMs into processor memory. See Table 4 for jumper settings. Note, the
evaluation module does not allow chip select ( CS) line of the converter to be assigned to different memory
locations. It is therefore suggested the CS line be grounded or wired to an appropriate signal of the user
processor.
Table 4. Jumper Settings
Reference Pins
Description
Designator
1–2 2–3
W1 Short U8 pin 14 to Powerdown/Reset signal Installed
(1)
Short U8 pin 13 to Powerdown/Reset signal Installed
W2 Short U8 pin 12 to CONVST signal Installed
(1)
Short U8 pin 11 to CONVST signal Installed
W3 Short U8 pin 10 to RD signal Installed
(1)
Short U8 pin 8 to RD signal Installed
W4 Short inverted BUSY to INTC Installed
(1)
Short BUSY to INTC Installed
W5 Short +5VD to +BVDD Installed
(1)
Short +3.3VD to +BVDD Installed
(1)
Factory set condition
The data bus is available at connector P3, see table 4 for pin out information.
Table 5. Data Bus Connector P3
Connector.Pin
(1)
Signal Description
P3.1 D0 Buffered Data Bit 0 (LSB)
P3.3 D1 Buffered Data Bit 1
P3.5 D2 Buffered Data Bit 2
P3.7 D3 Buffered Data Bit 3
P3.9 D4 Buffered Data Bit 4
P3.11 D5 Buffered Data Bit 5
P3.13 D6 Buffered Data Bit 6
P3.15 D7 Buffered Data Bit 7
P3.17 D8 Buffered Data Bit 8
P3.19 D9 Buffered Data Bit 9
P3.21 D10 Buffered Data Bit 10
P3.23 D11 Buffered Data Bit 11 (MSB - ADS7881)
P3.25 D12 Buffered Data Bit 12
P3.27 D13 Buffered Data Bit 13 (MSB - ADS7891)
P3.29 D14 Not connected
P3.31 D15 Not connected
(1)
All even numbered pins of P3 are tied to DGND.
ADS7881/ADS7891EVMSLAU150 – December 2004 5