Datasheet

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4.1 Signal Conditioning
130 pF
C0G
+2.5 V
THS4031
1000 pF
C0G
(+)IN
(−)IN
C35
C16
R13
U2
C33
R25
C7
C31
C37
C15
R10
R6
R1
R12
604 
−V
CC
0.1 F
1 F
604 
21 
21 
12 
1 F
0.1 F
+V
CC
1 F
V
IN
10 k
Analog Interface
Table 1. Analog Input Connector
Connector.Pin#
(1)
Signal Description
P1.2 +IN Non-inverting input channel
P1.4 Reserved
P1.6 Reserved
P1.8 Reserved
P1.10 Reserved
P1.12 Reserved
P1.14 Reserved
P1.16 Reserved
P1.18 Reserved
P1.20 REF+ External reference input
(1)
All odd numbered pins of P1 are tied to AGND.
The factory recommends the analog input to any SAR type converter be buffered and low pass filtered.
This input buffer on the ADS7881/ADS7891EVM utilizes the THS4031 configured as an INVERTING gain
of one, as shown in Figure 1 . It is important to note the amplifier is not stable at a gain of one, thus, it is
configured in for inverting gain of one. The THS4031 was selected for its low noise, high slew rate and
fast settling time. The low pass filter resistor and capacitor values were selected such that
ADS7881/ADS7891EVM would meet the 1MHz AC performance specifications listed in the datasheet. The
series resistor works in conjunction with the capacitor to filter the input signal, but also isolates the
amplifier from the capacitive load. The capacitor to ground at the input of the A/D works in conjunction
with the series resistor to filter the input signal, and acts like a charge reservoir. This external filter
capacitor works with the amplifier to charge the internal sampling capacitor during sampling mode.
Resistors R1 and R12 were selected to reduce offset.
The EVM has a provision to offset the input voltage by adjusting, R25, a 10k potentiometer.
Figure 1. ADS7881 Input Buffer Circuit
ADS7881/ADS7891EVMSLAU150 – December 2004 3