Datasheet


SLAS370C − APRIL 2002 − REVISED OCTOBER 2004
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9
Figure 9
−1
0
1
2
3
4
5
6
−6−5−4−3−2−10123456
V
DD
V
I
 x GAIN <V
DD
−1.4
Gain = 1
Gain = 20
Common-Mode Input Voltage − V
Differential Input Voltage − V
TYPICAL INPUT RANGE
V
DD
= 5 V,
T
A
= 25°C
Figure 10
0
1
2
3
4
5
6
012345
V
DD
Upper Compliance Limit
Lower Compliance Limit
Level-Shift Error
Input to A/D
Valid Bit = 1
− Output Voltage − V
PGA OUTPUT
V
O
| V
I
| x Gain
V
DD
= 5 V,
T
A
= 25°C
Figure 11
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
0 5 10 15 20 25 30 35 40 45 50
I
QUIESCENT CURRENT
vs
SAMPLING RATE
Sampling Rate − ks/s
SCLK = CCLK = 52 x Sampling Rate,
V
DD
= 5 V,
V
REF
and Buf on, OSC off,
T
A
= 25°C
Q
− Quiescent Current − mA
Figure 12
0
5
10
15
20
0 5 10 15 20
Peak-To-Peak Output Code Range
NOISE AND EFFECTIVE NUMBER OF BITS
vs
PGA GAIN
PGA Gain
Effective Number of Bits
15
14
13
12
11
CCLK = 2.5 MHz,
V
DD
= 5 V,
T
A
= 25°C
V
REF
= 2.5 V,
Internal Ref + Buf,
DC Input