Datasheet


SLAS370C − APRIL 2002 − REVISED OCTOBER 2004
www.ti.com
36
In Figure 42 the result of the just requested conversion is retrieved. The microcontroller must wait for BUSY
to go inactive before clocking out the ADC Output register. CS
must stay low while waiting for BUSY. This
example is for LS byte first, CCLK divider = 1, and SCLK active on the falling edge. Notice that the DOUT pin
is not driven with correct data until the appropriate active edge of SCLK.
1G2 M0
B5 B4 B3 B2 B1 B0 0 OVR B13 B12 B11 B10 B8
SCLK
CS
CCLK
DIN
DOUT
BUSY
B9 B7 B6
G1 G0 M3 M2 M1
Figure 42. Timing Diagram for Automatic Read Back of Current Conversion Result Using Mode 2
Mode 3
This mode only returns the most significant byte of the conversion. It is equivalent to an eight bit read from
ADDR = 1.