Datasheet

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SLAS370C − APRIL 2002 − REVISED OCTOBER 2004
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Mode 1
In this mode, the serial interface configures itself to clockout a conversion result as soon as a conversion is
started. This is useful since a read instruction is not required so eight SCLK cycles are saved. This mode
operates like an implied sixteen bit read instruction byte for ADDR = 1 was sent to the ADS7871 after starting
the conversion.
It is not necessary to wait for the end of the conversion to start clocking out conversion results. The last
completed conversion at the sampling edge of SCLK is read back (whether a conversion is in progress or not).
Mode 2
This mode is similar to Mode 1 except that the conversion result is provided LS byte first (equivalent to a sixteen
bit read from ADDR = 0).
Figure 41 and Figure 42 show timing examples of an automatic read back operation using mode 2. In Figure 41,
the result of the previous conversion is retrieved. This example is for LSB first, CCLK divider = 2, and SCLK
active on the rising edge. The data may be read back immediately after the start conversion instruction. It is
not necessary to wait for the conversion to actually start (or finish).
M0 M1
M2
M3 G0 G1 G2 1
OVR 0 B0 B1 B6 B7 B10
B13
SCLK
CS
CCLK
DIN
DOUT
BUSY
The remaining output bits loaded in the output registerFirst output bit loaded in the output register
B2 B3 B4 B5 B8 B9 B11 B12
Figure 41. Timing Diagram for Automatic Read Back of Previous Conversion Result Using Mode 2