Datasheet

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SLAS370C − APRIL 2002 − REVISED OCTOBER 2004
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34
STARTING A CONVERSION USING THE CONVERT PIN
A conversion can also be started by an active (rising) edge on the CONVERT pin. Similar to the CNV/BSY
register bit, the conversion starts on the second falling edge of CCLK after the CONVERT rising edge.
The CONVERT pin must stay high for at least two CCLK periods. CONVERT must also be low for at least two
CCLK periods before going high. BUSY goes active one DCLK period after the start of the conversion.
Contrary to the CNV/BSY bit in the register, the CONVERT pin aborts any conversion in process and
restart a new conversion. BUSY goes low at the end of the conversion. CS may be either high or low when
the CONVERT pin starts a conversion.
Figure 40 shows the timing of a conversion start using the CONVERT pin. The double falling arrow on CCLK
indicates when the conversion cycle actually starts (the second active CCLK edge after CONVERT goes
active). This example is for CCLK divider = 4. Notice that BUSY goes active four CCLK periods later.
Conversion Starts
CCLK
BUSY
CONV
Figure 40. Timing Diagram of Conversion Start Using CONVERT Pin
READ BACK MODES
There are four modes available to read the A/D conversion result from the A/D Output registers. The RBM1 and
RBM0 bits in the A/D Control register (ADDR = 3) control which mode is used by the ADS7871.
Read Back Mode 0 (default mode) requires a separate read instruction to retrieve the conversion result
Read Back Mode 1 (automatic) provides the output most significant byte first
Read Back Mode 2 (automatic) provides the output least significant byte first
Read Back Mode 3 (automatic) provides only the most significant byte
Mode 3 does not short cycle the A/D. Automatic read back mode is only triggered when starting a conversion
using the serial interface. Conversions started using the CONVERT pin do not trigger the read back mode.
The first bit of data for an automatic read back is loaded on the first active SCLK edge of the read portion of
THE instruction. The remaining bits are loaded on the next inactive SCLK edge (the first one after the first active
edge). To avoid getting one bit from one conversion and the remainder of the byte from another conversion,
a conversion should not finish between the first active SCLK edge and the next inactive edge.
Mode 0
Mode 0 (default operating mode) requires a read instruction to be performed to retrieve a conversion result.
MS byte first format is achieved by performing a sixteen bit read from ADDR = 1. LS byte first format is achieved
by performing a sixteen bit read from ADDR = 0. Reading only the most significant byte can be achieved by
performing an eight bit read from ADDR = 1.
To increase throughput it is possible to read the result of a conversion while a conversion is in progress. The
last conversion completed prior to the first active SCLK edge of the conversion data word (not the instruction
byte) is retrieved. This overlapping allows a sequence of start conversion N, read conversion N – 1, start
conversion N +1, read conversion N, etc. For conversion 0, the result of conversion –1 would need to be
discarded.