Datasheet
SLAS370C − APRIL 2002 − REVISED OCTOBER 2004
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33
Figure 38 shows an example of a conversion start using an 8-bit write operation to the Gain/Mux register with
the CNV/BSY bit set to 1. The double rising arrow on SCLK indicates where the data is latched into the Gain/Mux
register and the double arrow on CCLK indicates when the conversion starts. The example is for LSB first, CCLK
divider = 1, and SCLK active on the rising edge.
A0
A1 A2 A3 A4 0 0 0 M0 M1 M2 M3 G0 G1
SCLK
DIN
DOUT
CS
CCLK
BUSY
Conversion Starts
G2
1
Figure 38. Timing Diagram for a Conversion Start Using 8-Bit Write to the Gain/Mux Register
Figure 39 shows the timing of a conversion start using the convert start instruction byte when a conversion is
already in progress (indicated by BUSY high). The double rising arrow on SCLK indicates when the instruction
is latched. The second falling arrow on CCLK indicates when the conversion cycle would have started had a
conversion not been in progress. The double falling arrow on CCLK indicates where the conversion cycle
actually starts (immediately after completion of the previous conversion). This example is for LSB first, CCLK
divider = 2, and SCLK active on the rising edge. Notice that BUSY is low for two CCLK periods because the
CCLK divider = 2.
y
z
M0 M1 G0 1
Normal Start Delayed Start
SCLK
DIN
DOUT
CS
CCLK
BUSY
M2
G1
G2
M3
Figure 39. Timing Diagram of Delayed Conversion Start with Serial Interface