Datasheet
SLAS370C − APRIL 2002 − REVISED OCTOBER 2004
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32
STARTING A CONVERSION THROUGH THE SERIAL INTERFACE
There are two methods of starting a conversion cycle through the serial interface. The first (nonaddressed or
direct mode) is by using the start conversion byte as described earlier. The second (addressed mode) is by
setting the CNV/BSY bit of register 4 or register 5 by performing a write instruction.
The conversion starts on the second falling edge of DCLK after the eighth active edge of SCLK (for the
instruction in nonaddressed mode or the data in addressed mode). The BUSY pin goes active (1) one DCLK
period (1, 2, 4, or 8 CCLK periods depending on CFD1 and CFD0) after the start of a conversion. This delay
is to allow BUSY to go inactive when conversions are queued to follow in immediate succession. BUSY goes
inactive at the end of the conversion.
If a conversion is already in progress when the CNV/BSY bit is set on the eighth active SCLK edge, the
CNV/BSY bit is placed in the queue and the current conversion is allowed to finish. If a conversion is already
queued, the new one replaces the currently queued conversion. The queue is only one conversion long.
Immediately upon completion of the current conversion, the next conversion starts. This allows for maximum
throughput through the A/D converter. Since BUSY is defined to be inactive for the first DCLK clock period of
the conversion, the inactive (falling) edge of BUSY can be used to mark the end of a conversion (and start of
the next conversion).
Figure 37 shows the timing of a conversion start using the convert start instruction byte. The double rising arrow
on SCLK indicates when the instruction is latched. The double falling arrow on CCLK indicates where the
conversion cycle actually starts (second falling edge of CCLK after the eighth active edge of SCLK). This
example is for LSB first, CCLK divider = 1, and SCLK active on rising edge. Notice that BUSY goes active one
CCLK period later since CCLK divider = 1.
M0 M1 M2 M3 G0 G1
G2
1
Conversion Starts
SCLK
DOUT
CS
CCLK
BUSY
DIN
Figure 37. Timing Diagram for a Conversion Start Using Serial Interface Convert Instruction