Datasheet

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SLAS370C − APRIL 2002 − REVISED OCTOBER 2004
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31
Figure 35 shows the timing for entering the high impedance state when the 8051 bit is set. Notice that on the
last bit of the read operation the DIN (and DOUT) pin goes to the high impedance state on the active edge of
SCLK instead of waiting for the inactive edge of SCLK or CS
going high as shown in Figure 33 and Figure 34.
This is for compatibility with 80C51 mode 0 type serial interfaces. An 80C51 forces DIN valid before the SCLK
falling edge and holds it valid until after the SCLK rising edge. This can lead to contention but setting the 8051
bit fixes this potential problem without requiring CS to be toggled high after every read operation.
A0 A1 A2 A3 0 D0
D5
D0 D1
D2
D3 D4
D7
Micro drives DIN
ADS7871 drives DIN DIN high−impedance on active SCLK edge
SCLK
DIN
DOUT
CS
D6 D7
D5 D6
A4 0
1
D1 D2
D3
D4
Figure 35. Timing for High-Impedance State on DIN/DOUT (8051 Bit = 1)
ID Register
The ADS7871 has an ID register (at ADDR = 31) to allow the user to identify which revision of the ADS7871
is installed. This is shown in Figure 36.
ID REGISTER
ADDR D7 (MSB) D6 D5 D4 D3 D2 D1 D0
31 0 0 0 0 0 0 0 1
ADDR = 31
BIT SYMBOL NAME VALUE FUNCTION
D7−D0 — — — The contents of this register identify the revision of the ADS7871
Figure 36. ID Register (ADDR = 31)
Remaining Registers
The remaining register addresses are not used in the normal operation of the ADS7871. These registers return
random values when read and nonzero writes to these registers cause erratic behavior. Unused bits in the
partially used registers must always be written low.