Datasheet
SLAS370C − APRIL 2002 − REVISED OCTOBER 2004
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24
A/D Control Register
The A/D Control register (ADDR = 3) configures the CCLK divider and read back mode option as shown in
Figure 27.
ADC CONTROL REGISTER
ADDR D7 (MSB) D6 D5 D4 D3 D2 D1 D0
3 0 0 BIN 0 RBM1 RBM0 CFD1 CFD0
ADDR = 3
BIT SYMBOL NAME VALUE FUNCTION
D7−D6 — — 0 These bits are reserved and must always be written 0.
D5 BIN Output Data
Format
0
1
Mode 0 − Twos complement output data format
Mode 1 − Binary output data format
D4 — — 0 This is a reserve bit and must always be written 0
D3−D2 RBM1−RBM0 Automatic Read
Back Mode
00
01
10
11
Mode 0 − Read instruction required to access ADC conversion result.
Mode 1 − Most significant byte returned first
Mode 2 − Least significant byte returned first
Mode 3 − Only most significant byte returned
D1−D0 CFD1−CFD0 CCLK Divide 00
01
10
11
Division factor for CCLK = 1 (DCLK = CCLK)
Division factor for CCLK = 2 (DCLK = CCLK/2)
Division factor for CCLK = 4 (DCLK = CCLK/4)
Division factor for CCLK = 8 (DCLK = CCLK/8)
Bold items are power-up default conditions.
Figure 27. ADC Control Register (ADDR = 3)
Read Back Modes
RBM1 and RBM0 determine which of four possible modes is used to read the A/D conversion result from the
A/D Output registers.
D Mode 0 (default mode) requires a separate read instruction to be performed in order to read the output
of the A/D Output registers
D Mode 1, 2, and 3: Provide for different types of automatic read-back options of the conversion results from
the A/D Output registers without having to use separate read instructions:
Mode 1: Provides data MS byte first
Mode 2: Provides data LS byte first
Mode 3: Output only the MS byte
For more information refer to the read back mode section.
Clock Divider
CFD1 and CFD0 set the CCLK divisor constant which determines the DCLK applied to the A/D, PGA, and
reference. The A/D and PGA operate with a maximum clock of 2.5 MHz. In situations where an external clock
is used to pace the conversion process it may be desirable to reduce the external clock frequency before it is
actually applied to the PGA and A/D. The signal that is actually applied to the A/D and PGA is DCLK, where
DCLK = CCLK/DF (DF is the division factor determined by the CFD1 and CFD0 bits). For example, if the
external clock applied to CCLK is 10 MHz and DF = 4 (CFD1 = 1, CFD0 = 0), DCLK equals 2.5 MHz.